| US 7,480,809 B2 | ||
| Reducing power consumption of a microprocessor | ||
| Parag Naik, Karnataka State (India) | ||
| Assigned to Genesis Microchip Inc., Santa Clara, Calif. (US) | ||
| Filed on Oct. 13, 2005, as Appl. No. 11/251,586. | ||
| Claims priority of provisional application 60/619060, filed on Oct. 15, 2004. | ||
| Prior Publication US 2006/0101297 A1, May 11, 2006 | ||
| Int. Cl. G06F 1/00 (2006.01) | ||
| U.S. Cl. 713—300 [713/320; 717/139] | 10 Claims |
| 1. A computer-implemented method for reducing power consumption of a microprocessor, the method comprising:
profiling one or more signal transitions associated with instructions in an instruction set of a microprocessor;
assigning a probability of occurrence to each of one or more instructions in the instruction set; and
assigning a binary operation code to at least one instruction of the one or more instructions in the instruction set based
on the absolute probability of occurrence for the at least one instruction relative to the probabilities of occurrence of
at least all of the other instructions of the one or more instructions, wherein instructions having the highest absolute probabilities
of occurrence are assigned operation codes that require fewer signal transitions, whereby the power consumption of the microprocessor
is reduced.
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