| US 7,480,781 B2 | ||
| Apparatus and method to merge and align data from distributed memory controllers | ||
| Rohit Natarajan, Sunnyvale, Calif. (US); Sridhar Lakshmanamurthy, Sunnyvale, Calif. (US); and Chen-Chi Kuo, Pleasanton, Calif. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Dec. 30, 2004, as Appl. No. 11/26,653. | ||
| Prior Publication US 2006/0149872 A1, Jul. 06, 2006 | ||
| Int. Cl. G06F 7/14 (2006.01) | ||
| U.S. Cl. 711—170 [711/5; 711/201] | 6 Claims |
| 1. A memory controller comprising:
an interleave circuit to receive a memory access command from a memory master over a bus; and
a scoreboard free-list populated with at least one scoreboard entry to indicate data was retrieved from distributed memory
responsive to the memory access command,
wherein the interleave circuit is to cause a push arbiter, coupled between the interleave circuit and the memory master, to
align the retrieved data based on a corresponding scoreboard entry.
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