US 7,480,772 B2
Data processing system and method for efficient communication utilizing an Tn and Ten coherency states
James Stephen Fields, Jr., Austin, Tex. (US); Benjiman Lee Goodman, Cedar Park, Tex. (US); Guy Lynn Guthrie, Austin, Tex. (US); William John Starke, Round Rock, Tex. (US); and Derek Edward Williams, Austin, Tex. (US)
Assigned to International Business Machines Corporation, Armonk, N.Y. (US)
Filed on Aug. 08, 2007, as Appl. No. 11/835,984.
Application 11/835984 is a continuation of application No. 11/055476, filed on Feb. 10, 2005, granted, now 7,454,577.
Prior Publication US 2008/0040556 A1, Feb. 14, 2008
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/00 (2006.01)
U.S. Cl. 711—144  [711/119; 711/141] 7 Claims
OG exemplary drawing
 
1. A method of data processing in a cache coherent data processing system including at least first and second coherency domains, wherein the first coherency domain includes at least first and second cache memories and the second coherency domain includes at least a third cache memory, said method comprising:
in the first cache memory within said first coherency domain of said data processing system, said first cache memory including a data array and a cache directory, holding a memory block in a storage location of the data array associated with both an address tag in the cache directory and a coherency state field in the cache directory, wherein said memory block held in the data array of the first cache memory is concurrently cacheable in both the first and second coherency domains; and
setting said coherency state field of the cache directory to a state among a plurality of states that indicates that said memory block is possibly shared with the second cache memory in said first coherency domain and cached only within said first coherency domain.