| US 7,480,348 B2 | ||
| I/Q demodulation circuit | ||
| Yoshiaki Nakano, Osaka (Japan) | ||
| Assigned to Sharp Kabushiki Kaisha, Osaka (Japan) | ||
| Filed on Aug. 17, 2004, as Appl. No. 10/919,441. | ||
| Claims priority of application No. 2003-294067 (JP), filed on Aug. 18, 2003. | ||
| Prior Publication US 2005/0041759 A1, Feb. 24, 2005 | ||
| Int. Cl. H04L 27/00 (2006.01) | ||
| U.S. Cl. 375—324 [329/323; 329/318; 329/349; 329/359] | 12 Claims |

| 1. An I/Q demodulation circuit comprising:
an I/Q demodulator for producing an analog I/Q signal by multiplying an input signal by a local oscillation signal;
an analog-to-digital converter for converting the analog I/Q signal into a digital I/Q signal;
a reference sinusoidal-wave signal generator for producing a predetermined reference sinusoidal-wave signal;
a selector for selecting and feeding to the I/Q demodulator one of an external input signal and the reference sinusoidal-wave
signal;
an offset amount detection circuit for detecting a DC offset amount and a phase offset amount of the digital I/Q signal obtained
when the reference sinusoidal-wave signal is selected;
a storage circuit for storing a result of detection by the offset amount detection circuit or a correction value with which
to correct for the result; and
an offset correction circuit for correcting for, based on data stored in the storage circuit, a DC offset and a phase offset
of the digital I/Q signal obtained when the external input signal is selected,
wherein the offset amount detection circuit includes:
a delay circuit for producing a delayed inverted signal by delaying, of two versions of the digital I/Q signal differentially
fed thereto, an inverted digital I/Q signal by a half period; and
a subtraction circuit for determining the DC offset amount by subtracting the delayed inverted signal from a non-inverted
digital I/Q signal.
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