| US 7,479,823 B2 | ||
| Multiple circuit blocks with interblock control and power conservation | ||
| Tadashi Hoshi, Higashimurayama (Japan); Kenji Hirose, Tokorozawa (Japan); Hideaki Abe, Higashiyamato (Japan); Junichi Nishimoto, Hachioji (Japan); and Midori Nagayama, Kodaira (Japan) | ||
| Assigned to Renesas Technology Corp., Tokyo (Japan) | ||
| Filed on Jan. 27, 2006, as Appl. No. 11/340,488. | ||
| Application 10/633567 is a division of application No. 10/081186, filed on Feb. 25, 2002, granted, now 6,639,454. | ||
| Application 11/340488 is a continuation of application No. 11/015649, filed on Dec. 20, 2004, granted, now 7,078,959. | ||
| Application 11/015649 is a continuation of application No. 10/633567, filed on Aug. 05, 2003, granted, now 6,853,239. | ||
| Claims priority of application No. 2001-284383 (JP), filed on Sep. 19, 2001. | ||
| Prior Publication US 2006/0132228 A1, Jun. 22, 2006 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G11C 5/14 (2006.01) | ||
| U.S. Cl. 327—545 [327/594; 365/229] | 3 Claims |
| 1. A data processor comprising:
a first circuit including a central processing unit which executes a plurality of instructions;
a second circuit coupled to said first circuit via a holding module and a switch module, and
a mode control circuit controlling said switch module according to operational mode including a first mode and a second mode,
wherein said second circuit includes an input/output circuit which couples to said first circuit via data signal lines,
wherein said holding module is arranged on said data signal lines,
wherein said data processor includes a first area including said first circuit, and a second area including said second circuit,
said holding module and said switch module,
wherein said first area and said second area are supplied an operational potential in said first mode,
wherein said first area is cut off from said operational potential and said second area is supplied said operational potential
in said second mode, and
wherein said input/output circuit receives data signals from said holding module via said data signal lines in said second
mode.
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