| US 7,479,683 B2 | ||
| Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics | ||
| Nestor A. Bojarczuk, Jr., Poughkeepsie, N.Y. (US); Cyril Cabral, Jr., Mahopac, N.Y. (US); Eduard A. Cartier, New York, N.Y. (US); Matthew W. Copel, Yorktown Heights, N.Y. (US); Martin M. Frank, New York, N.Y. (US); Evgeni P. Gousev, Mahopac, N.Y. (US); Supratik Guha, Chappaqua, N.Y. (US); Rajarao Jammy, Hopewell Junction, N.Y. (US); Vijay Narayanan, New York, N.Y. (US); and Vamsi K. Paruchuri, New York, N.Y. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Oct. 01, 2004, as Appl. No. 10/957,342. | ||
| Application 10/957342 is a continuation in part of application No. 10/863830, filed on Jun. 04, 2004. | ||
| Prior Publication US 2005/0269635 A1, Dec. 08, 2005 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H01L 29/94 (2006.01); H01L 29/76 (2006.01) | ||
| U.S. Cl. 257—410 [257/368; 257/369; 257/528; 257/E21.636; 257/E21.639; 438/107; 438/592] | 17 Claims |
| 1. A semiconductor structure comprising:
a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of said source
and drain diffusion regions is separated by a device channel; and
a first gate stack of a pFET device located on top of some of said device channels, said first gate stack of said pFET device
comprising a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate
electrode abutting the insulating interlayer, said insulating interlayer comprises an insulating metal nitride that stabilizes
threshold voltage and flatband voltage of said p-FET device to a targeted value and is one of aluminum oxynitride (AlOxNy), boron nitride (BN), boron oxynitride (BOxNy), gallium nitride (GaN), gallium oxynitride (GaON), indium nitride (InN) and indium oxynitride (InON); and
a second gate stack of an nFET device located on top remaining device channels, said second gate stack of said n-FET device
comprising a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric.
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