	US 7,479,681 B2
	Multilayered semiconductor structure containing a MISFET, a resistor, a capacitor, and an inductor
Fumitaka Nakayama, Higashikurume (Japan); Masatoshi Morikawa, Hanno (Japan); Yutaka Hoshino, Akishima (Japan); and Tetsuo Uchiyama, Maebashi (Japan)
Assigned to Renesas Eastern Technology Corp., Tokyo (Japan)
Filed on Apr. 12, 2007, as Appl. No. 11/783,779.
Application 11/783779 is a division of application No. 11/493829, filed on Jul. 27, 2006, granted, now 7,217,987.
Application 11/493829 is a continuation of application No. 10/670258, filed on Sep. 26, 2003, granted, now 7,087,977.
Claims priority of application No. 2002-282366 (JP), filed on Sep. 27, 2002; and application No. 2002-377030 (JP), filed on Dec. 26, 2002.
Prior Publication US 2007/0194407 A1, Aug. 23, 2007
Int. Cl. H01L 23/62 (2006.01)

U.S. Cl. 257—379 [257/528]

1 Claim

1. A semiconductor device comprising, over a semiconductor substrate:

a MISFET including a source, a drain, and a gate electrode;

a resistor element;

a first capacitor element including a first lower electrode and a first upper electrode;

a second capacitor element including a second lower electrode and a second upper electrode; and

an inductor,

wherein a first silicon layer and a second silicon layer disposed over the first silicon layer are formed over the semiconductor substrate,

wherein a first metal layer, a second metal layer disposed over the first metal layer and a third metal layer disposed over the second metal layer are formed over the semiconductor substrate,

wherein the first silicon layer forms the first lower electrode of the first capacitor element and the resistor element,

wherein the second silicon layer forms the first upper electrode of the first capacitor element and the gate electrode of the MISFET, and

wherein the first metal layer forms the second lower electrode of the second capacitor element, the second metal layer forms the second upper electrode of the second capacitor element, and the third metal layer forms the inductor.