| US 7,479,674 B2 | ||
| Field effect transistor | ||
| Yukio Nakabayashi, Yokohama (Japan); Kazumi Nishinohara, Yokohama (Japan); Atsuhiro Kinoshita, Kamakura (Japan); and Junji Koga, Yokosuka (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Feb. 21, 2008, as Appl. No. 12/34,822. | ||
| Application 12/034822 is a division of application No. 11/081348, filed on Mar. 16, 2005, granted, now 7,358,550. | ||
| Claims priority of application No. 2004-092537 (JP), filed on Mar. 26, 2004. | ||
| Prior Publication US 2008/0150040 A1, Jun. 26, 2008 | ||
| Int. Cl. H01L 29/76 (2006.01) | ||
| U.S. Cl. 257—288 [257/369] | 11 Claims |
| 1. A field effect transistor comprising;
a first semiconductor region forming a channel region;
a gate electrode insulatively disposed over the first semiconductor region;
source and drain electrodes sandwiching the first semiconductor region in a channel-length direction; and
second semiconductor regions each having impurity concentration higher than that of the first semiconductor region, one of
the second semiconductor regions being formed between the first semiconductor region and the source electrode and another
of the second semiconductor regions being formed between the first semiconductor region and the drain electrode, wherein
the source and drain electrodes are offset to the gate electrode in a direction in which the source and drain electrodes are
separated from each other in a channel direction, and
the second semiconductor regions each have a thickness not more than a thickness with which they are substantially completely
depleted with the source and drain electrodes being in thermal equilibrium with the second semiconductor regions.
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