US 7,478,302 B2
	Signal integrity self-test architecture
Hendricus Joseph Maria Veendrick, Eindhoven (Netherlands)
Assigned to NXP B.V., Eindhoven (Netherlands)
Appl. No. 10/557,679 PCT Filed May 18, 2004, PCT No. PCT/IB2004/050731 § 371(c)(1), (2), (4) Date Nov. 22, 2005, PCT Pub. No. WO2004/106957, PCT Pub. Date Dec. 09, 2004.
Claims priority of application No. 03101562 (EP), filed on May 28, 2003.
Prior Publication US 2007/0079188 A1, Apr. 05, 2007
Int. Cl. G01R 31/28 (2006.01)

U.S. Cl. 714—734  [714/733; 714/22; 714/30; 714/45; 714/46; 714/721; 714/724; 714/740; 714/745; 702/130; 702/183; 374/150]

39 Claims

1. A method of testing an integrated circuit device comprising a module, a module monitor incorporated into the module and being operable to produce a measurement signal indicative of an operating parameter of the module concerned, the method including receiving the measurement signal from the module monitor and processing that received signal to produce a test result, the operating parameter of the module concerned including one or more of temperature, cross-talk, supply noise, or matching.