| US 7,478,280 B2 | ||
| Test system for integrated circuits | ||
| Alvar A. Dean, Essex Junction, Vt. (US); and Sebastian T. Ventrone, South Burlington, Vt. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Dec. 13, 2007, as Appl. No. 11/955,433. | ||
| Application 11/955433 is a continuation of application No. 09/394302, filed on Sep. 10, 1999, granted, now 7,350,108. | ||
| Prior Publication US 2008/0091994 A1, Apr. 17, 2008 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G06F 11/00 (2006.01) | ||
| U.S. Cl. 714—27 [702/118; 206/706] | 7 Claims |
| 1. A method for simultaneously transporting and testing integrated circuit chips comprising:
connecting integrated circuit chips to test boards having test circuitry;
mounting said test boards in test boxes having power supplies;
mounting said test boxes in an in-transit box;
transporting said integrated circuit chips in said in-transit box;
testing said integrated circuit chips during said transporting by using said test circuitry; and
supplying power to said integrated circuit chips during said transporting and said testing by using said power supplies.
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