| US 7,477,217 B2 | ||
| D/A converter circuit, organic EL drive circuit and organic EL display device | ||
| Jun Maede, Kyoto (Japan); Shinichi Abe, Kyoto (Japan); and Akio Fujikawa, Kyoto (Japan) | ||
| Assigned to Rohm Co., Ltd., Kyoto (Japan) | ||
| Filed on Sep. 24, 2004, as Appl. No. 10/948,237. | ||
| Claims priority of application No. 2003-339531 (JP), filed on Sep. 30, 2003. | ||
| Prior Publication US 2005/0067969 A1, Mar. 31, 2005 | ||
| Int. Cl. G09G 3/30 (2006.01) | ||
| U.S. Cl. 345—76 [341/135] | 2 Claims |

| 1. An organic EL drive circuit comprising:
a D/A converter circuit including a current mirror circuit, wherein said current mirror circuit including a plurality of transistor
cells, each said transistor cell including a first MOS transistor;
wherein said transistor cells comprise a series circuit of said first MOS transistor and a second transistor operable as a
switch circuit;
wherein said first MOS transistors is a serpentine MOS transistor, said second transistor operable as the switch circuit is
a second MOS transistor and said serpentine MOS transistor and said second MOS transistor are formed in a rectangular region
in plan view;
wherein said transistor cells are assigned as input side transistor cell of said current mirror circuit and a plurality of
output side transistor cells of said current mirror circuit, said transistors operable as switch circuits of the plurality
of said output side transistor cells being turned ON/OFF in response to 1 bit of display data supplied to gates thereof to
generate analog current obtained by D/A conversion of the display data as a total output of said output side transistor cells;
wherein the analog current is an output current to be supplied to terminal pins of an organic EL display panel or a base current
on which the output current is generated:
wherein said transistor cell is selected from transistor cells arranged in a matrix in a rectangular transistor arranging
block; and
wherein said rectangular transistor arranging block has a width in a pad arranging direction substantially corresponding to
3n times a pad pitch in the pad arranging direction, where n is a positive integer, 4 or more of said transistor cells are
arranged for the width, a number of said transistor cells are arranged in a direction perpendicular to the pad arranging direction,
said transistor cells are selected such that said D/A converter circuits for R, G and B in said transistor arranging block
are sequentially formed in a direction perpendicular to said pad arranging direction as an IC.
|