| US 7,477,071 B2 | ||
| Three input field programmable gate array logic circuit configurable as a three input look up table, a D-latch or a D flip-flop | ||
| Alan B. Reynolds, Long Valley, N.J. (US); Andrew W. Reynolds, Stanhope, N.J. (US); and Volker Hecht, Barsinghausen (Germany) | ||
| Assigned to Actel Corporation, Mountain View, Calif. (US) | ||
| Filed on Mar. 11, 2008, as Appl. No. 12/46,160. | ||
| Application 12/046160 is a continuation of application No. 11/426158, filed on Jun. 23, 2006, granted, now 7,365,567. | ||
| Application 11/426158 is a continuation of application No. 10/877872, filed on Jun. 24, 2004, granted, now 7,106,100. | ||
| Application 10/877872 is a continuation of application No. 10/137729, filed on May 01, 2002, granted, now 6,777,977. | ||
| Prior Publication US 2008/0150580 A1, Jun. 26, 2008 | ||
| Int. Cl. G06F 7/38 (2006.01); H03K 19/173 (2006.01) | ||
| U.S. Cl. 326—38 [326/40; 326/46] | 20 Claims |
| 1. A programmable logic cell, capable of receiving a first input signal, a second input signal, and a third input signal,
and providing an output signal, comprising:
a first multiplexer having a first input, a second input, an output, and a selector;
a NAND gate having a first input, a second input, and an output, wherein the first input of the NAND gate receives the output
from the first multiplexer;
a second multiplexer having a first input, a second input, an output, and a selector;
a third multiplexer having a first input coupled to the output of the second multiplexer, a second input, an output providing
the output signal for the programmable logic cell, and a selector;
a plurality of programmable elements coupled to the first multiplexer, the second multiplexer, and the third multiplexer such
that the combination of the first multiplexer, the second multiplexer, the third multiplexer, and the NAND gate together perform
each one of a set of functions depending on which of the plurality of programmable elements are programmed, said set of functions
comprising:
a D flip-flop,
a D latch, and
a LUT capable of implementing any three input logic function.
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