	US 7,476,915 B2
	Semiconductor integrated circuit including a first region and a second region
Masayuki Ohayashi, Ome (Japan); and Takashi Yokoi, Kodaira (Japan)
Assigned to Renesas Technology Corp., Tokyo (Japan)
Filed on Feb. 29, 2008, as Appl. No. 12/40,127.
Application 12/040127 is a division of application No. 11/520622, filed on Sep. 14, 2006, granted, now 7,365,376.
Application 11/520622 is a division of application No. 10/431398, filed on May 08, 2003, granted, now 7,119,383.
Claims priority of application No. 2002-133674 (JP), filed on May 09, 2002.
Prior Publication US 2008/0157381 A1, Jul. 03, 2008
Int. Cl. H01L 27/10 (2006.01); H01L 29/73 (2006.01)

U.S. Cl. 257—207 [257/208; 257/210; 257/E27.105; 257/E27.108]

7 Claims

1. A semiconductor integrated circuit which is formed on one semiconductor substrate in a form so that the semiconductor integrated circuit includes a first region and a second region, which is different from the first region,

wherein a plurality of first cells having respectively given functions are arranged in the first region, lines which are arranged on peripheral portions of a first cell are laid out at positions away from boundaries of the first cells which are arranged close to each other, and

wherein a plurality of second cells having respectively given functions are arranged in the second region, a second cell includes wide-width lines arranged on the peripheral portion thereof and narrow-width lines having a line width narrower than the line width of the wide-width lines in the second cell, and the line interval between a wide-width line and a narrow-width line, which is arranged close to the wide-width line, is set to be wider than the minimum arrangement pitch of the narrow-width lines.