| US 7,476,626 B2 | ||
| Etch stop layer for a metallization layer with enhanced etch selectivity and hermeticity | ||
| Joerg Hohage, Dresden (Germany); Matthias Lehr, Dresden (Germany); and Volker Kahlert, Dresden (Germany) | ||
| Assigned to Advanced Micro Devices, Inc., Austin, Tex. (US) | ||
| Filed on Jun. 28, 2006, as Appl. No. 11/426,970. | ||
| Claims priority of application No. 10 2005 052 053 (DE), filed on Oct. 31, 2005. | ||
| Prior Publication US 2007/0096108 A1, May 03, 2007 | ||
| Int. Cl. H01L 21/31 (2006.01) | ||
| U.S. Cl. 438—763 [438/702; 438/724] | 14 Claims |
| 1. A method, comprising:
forming a dielectric barrier layer stack over a substrate having formed thereon a metal region, said dielectric barrier layer
stack comprising a first dielectric layer having a first thickness and a first relative permittivity and being formed on said
metal region, said dielectric barrier layer stack further comprising a second dielectric layer formed on said first dielectric
layer, said second dielectric layer having a first nitrogen content, a second relative permittivity, and a second thickness,
said second thickness being greater than said first thickness, said second relative permittivity being less than said first
relative permittivity;
forming a third dielectric layer above said second dielectric layer, said third dielectric layer having a second nitrogen
content less than the first nitrogen content; and
forming a low-k dielectric layer over said dielectric barrier layer stack.
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