| US 7,476,564 B2 | ||
| Flip-chip packaging process using copper pillar as bump structure | ||
| Chien-Fan Chen, Kaohsiung (Taiwan); and Yi-Hsin Chen, Kaohsiung (Taiwan) | ||
| Assigned to Advanced Semiconductor Engineering Inc., Kaohsiung (Taiwan) | ||
| Filed on Dec. 30, 2005, as Appl. No. 11/320,786. | ||
| Claims priority of application No. 94130921 A (TW), filed on Sep. 08, 2005. | ||
| Prior Publication US 2007/0052109 A1, Mar. 08, 2007 | ||
| Int. Cl. H01L 21/00 (2006.01); H01L 23/48 (2006.01); B23K 31/02 (2006.01) | ||
| U.S. Cl. 438—107 [438/108; 438/612; 438/613; 228/178; 228/180.1; 228/180.21; 228/180.22; 257/737; 257/762; 257/779; 257/780; 257/E23.021] | 5 Claims |
| 1. A flip-chip packaging process, comprising:
providing a wafer, wherein a bond pad and a passivation layer are formed sequentially on the wafer, the passivation layer
exposing a portion of the bond pad;
forming an under bump metallurgy (UBM) layer over the bond pad and the passivation layer;
forming a photoresist layer on the UBM layer with an opening formed for exposing a portion of the UBM layer;
filling a copper material into the opening;
removing the photoresist layer and the other portion of the UBM layer that is not covered by the copper material, thereby
forming a copper pillar having a plurality of external surfaces;
forming a solder on a substrate; and
embedding the copper pillar in the solder without a reflow step, wherein the solder covers substantially all of the external
surfaces of the copper pillar.
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