| US 7,475,269 B2 | ||
| Method and system for fast frequency switch for a power throttle in an integrated device | ||
| Kiran Padwekar, San Jose, Calif. (US); Arvind Mandhani, Washington, D.C. (US); and Durgesh Srivastava, Santa Clara, Calif. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Sep. 22, 2006, as Appl. No. 11/525,781. | ||
| Application 11/525781 is a division of application No. 10/794735, filed on Mar. 03, 2004, granted, now 7,272,736, filed on Sep. 18, 2007. | ||
| Prior Publication US 2007/0016819 A1, Jan. 18, 2007 | ||
| Int. Cl. G06F 1/12 (2006.01) | ||
| U.S. Cl. 713—400 [713/501; 326/93; 327/141; 327/145] | 19 Claims |
| 1. A method for generating a first clock signal comprising:
generating the first clock signal in a first clock domain that has a phase relationship with a second clock signal;
changing a current ratio of frequency between the first clock signal and the second clock signal to a different ratio; and
generating a synchronization signal for interfacing between a first component and a bus at a changed value for the different
ratio, including assigning a value of a counter to an updated reload value if the counter value is zero and a switch signal
for changing the current ratio is active, and generating the synchronization signal when the counter value is zero.
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