| US 7,475,193 B2 | ||
| Separate data and coherency cache directories in a shared cache in a multiprocessor system | ||
| David S. Hutton, Poughkeepsie, N.Y. (US); Kathryn M. Jackson, Poughkeepsie, N.Y. (US); Keith N. Langston, Woodstock, N.Y. (US); Pak-kin Mak, Poughkeepsie, N.Y. (US); and Bruce Wagar, Tempe, Ariz. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Jan. 18, 2006, as Appl. No. 11/334,280. | ||
| Prior Publication US 2007/0168619 A1, Jul. 19, 2007 | ||
| Int. Cl. G06F 12/00 (2006.01) | ||
| U.S. Cl. 711—130 [711/122] | 19 Claims |
| 1. A multiprocessor system comprising:
a plurality of processors; a main memory; and at least one shared cache memory;
said shared cache memory including shared control logic; a dual system directory structure having two system shared cache
directories including a shared superset cache directory and a shared subset cache directory for performing the role of L2 system cache directories for data, and system control for coherency; and a shared data array;
bidirectional control and data busses interconnecting said processors with said shared cache memory;
bidirectional control and data busses interconnecting said shared superset cache directory with said shared control logic
and said shared data array;
a unidirectional control bus connecting from said shared superset cache directory to said shared subset cache directory and
no data bus connecting to said shared subset cache directory;
a bidirectional control bus interconnecting said shared subset directory and said shared control logic;
bidirectional control and data busses interconnecting said shared superset cache directory and said main memory;
no data bus or control bus between said L2 subset cache directory and said shared data array or said main memory, and
in response to an entry being removed from said shared cache memory, said superset directory entry is not invalidated and
is instead migrated into said shared subset cache directory.
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