| US 7,474,716 B2 | ||
| Data recovery circuits using oversampling for maverick edge detection/suppression | ||
| Vincent Vallet, Mennecy (France); and Didier Malcavet, Champceuil (France) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Jul. 07, 2005, as Appl. No. 11/160,755. | ||
| Claims priority of application No. 04300431 (EP), filed on Jul. 08, 2004. | ||
| Prior Publication US 2006/0008040 A1, Jan. 12, 2006 | ||
| Int. Cl. H03D 1/00 (2006.01) | ||
| U.S. Cl. 375—340 [375/354; 375/375; 375/371; 375/373; 375/376; 375/316; 375/219; 341/143; 455/403] | 20 Claims |
| 1. An improved data recovery circuit for recovering the data sample in a set of data samples obtained by oversampling the
data to recover in an incoming stream of data bits in which the maverick data edge are detected and suppressed comprising:
a data input for receiving said incoming stream of data bits serially transmitted on a high speed communication link with
jitter and skew at a specified data rate synchronous with a reference clock;
oversampling means coupled to said data input to sample the data bits to recover by the n phases (C1, . . . , Cn) of said reference clock signal generated by a multiphase clock signal generator to produce a set of data samples D1, . . . , Dn) during each reference clock period;
edge detection means coupled to said oversampling means and configured to compare at least two consecutive data samples and
to generate a corresponding set of signals (E1, . . . , En) representing the data edge information indicative of the data edge or transition positions, so that when a data edge is
detected between said at least two consecutive data samples, the data edge information signal is at a determined binary logic
level and at the opposite binary logic level otherwise;
first memory means coupled to said edge detection means and configured to collect the data edge information in a corresponding
set of signals (E′1, . . . , E′n) presented in the form of a map of n bits for an extended period of time, the data edge information signal is at a first
binary logic level for detected data edges and at a second binary logic level otherwise, wherein the last bit map position
is considered as adjacent to the first bit map position, and conversely;
maverick edge detection/suppression means coupled to said first memory means;
selection determination means coupled to said maverick edge detection/suppression means and configured to use the memorized
data edge information signals to generate selection signals (S1, . . . , Sn) by locating a zone filled with binary values representative of said second binary logic level in said bit map and reducing
its width by performing successive iterations alternatively on the two sides of the zone until it only contains one value
at said second binary logic level, which points to the center of the zone where no data edge was detected, thereby selecting
the corresponding data sample which is the farthest of the data edge positions;
selection validation means coupled to said selection determination means to validate said selection signals and generating
validated selection signals (VS1, . . . , VSn) to avoid false determination due to jitter/skew;
second memory means coupled to said selection validation means to memorize the validated values of said selection signals
in a corresponding set of signals (MVS1, . . . , MVSn); and,
data sample selection means coupled to said oversampling means to receive the data samples (D1, . . . , Dn) and to said second memory means to receive said memorized values of validated selection signals (MVS1, . . . , MVSn) to generate the recovered data (RD).
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