| US 7,474,687 B1 | ||
| Staged correlator | ||
| Robert Mack, San Jose, Calif. (US); and Peter Vavaroutsos, San Jose, Calif. (US) | ||
| Assigned to Cypress Semiconductor Corp., San Jose, Calif. (US) | ||
| Filed on Dec. 17, 2004, as Appl. No. 11/15,105. | ||
| Claims priority of provisional application 60/532752, filed on Dec. 23, 2003. | ||
| Int. Cl. H04B 1/00 (2006.01) | ||
| U.S. Cl. 375—142 [375/150; 375/343] | 20 Claims |
| 1. A correlator, comprising:
a feedback circuit having a first input coupled to an incoming data stream, at least a second input and an output;
a data register to store an incoming data stream having a number of candidate bits, the data register having an output coupled
to the second input of the feedback circuit, the output to provide a feedback stream to the second input wherein the feedback
circuit is configured to toggle between outputting a bit of the incoming data stream to the data register and outputting a
bit of the feedback stream to the data register resulting in an interleaved data stream in the data register;
a code register to store a known code having a predetermined number of code chips; and
a comparator to compare a portion of the incoming data stream to a portion of the known code.
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