| US 7,474,558 B2 | ||
| Gated diode nonvolatile memory cell array | ||
| Yi Ying Liao, Sijhih (Taiwan); Wen Jer Tsai, Hualien (Taiwan); and Chih Chieh Yeh, Taipei (Taiwan) | ||
| Assigned to Macronix International Co., Ltd., Hsinchu (Taiwan) | ||
| Filed on Oct. 01, 2007, as Appl. No. 11/865,616. | ||
| Application 11/865616 is a continuation of application No. 11/298912, filed on Dec. 09, 2005, granted, now 7,283,389. | ||
| Prior Publication US 2008/0019172 A1, Jan. 24, 2008 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G11C 11/36 (2006.01) | ||
| U.S. Cl. 365—175 [365/185.01; 365/185.18; 257/104] | 16 Claims |
| 1. A semiconductor device comprising:
interlayer conductor connecting a plurality of arrays deposited in different layers;
the plurality of arrays separated by insulating layers respectively, each of said arrays comprising:
a plurality of conducting lines connecting to said interlayer conductor; and
a plurality of cells arranged in rows and columns, each of said cells comprising:
a junction device; and
a charge storage element sandwiched by said junction device and one corresponding conducting line of said plurality of conducting
lines,
wherein a single said junction device and said corresponding conducting line are sufficient to provide biases reversibly altering
said charge storage element among states and sensing said states.
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