| US 7,474,121 B1 | ||
| Configurable memory design for masked programmable logic | ||
| David A. Asson, Palo Alto, Calif. (US); and James Macarthur, Santa Clara, Calif. (US) | ||
| Assigned to Altera Corporation, San Jose, Calif. (US) | ||
| Filed on Dec. 13, 2005, as Appl. No. 11/302,696. | ||
| Application 11/302696 is a continuation of application No. 10/269113, filed on Oct. 09, 2002, granted, now 7,000,165. | ||
| Application 10/269113 is a continuation of application No. 09/302053, filed on Apr. 29, 1999, granted, now 6,492,833. | ||
| Claims priority of provisional application 60/083632, filed on Apr. 30, 1998. | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H01L 25/00 (2006.01); G01R 31/28 (2006.01); H03K 19/177 (2006.01) | ||
| U.S. Cl. 326—41 [714/733] | 12 Claims |
| 1. A programmable logic integrated circuit, the programmable logic integrated circuit comprising:
a read only memory (ROM);
a plurality of random access memory (RAM) blocks, wherein the RAM blocks are used individually or combined to form a larger
memory;
a RAM coupled to the ROM and comprising one or more of the plurality of RAM blocks; and
a controller coupled to the ROM, wherein the controller, after a reset condition, directs a clear of the RAM or a preload
of contents of the ROM to the RAM.
|