| US 7,473,952 B2 | ||
| Memory cell array and method of manufacturing the same | ||
| Dirk Manger, Dresden (Germany); Stefan Slesazeck, Dresden (Germany); Stefan Tegen, Dresden (Germany); Klaus Muemmler, Dresden (Germany); and Alexander Sieck, Dresden (Germany) | ||
| Assigned to Infineon Technologies AG, Neubiberg (Germany) | ||
| Filed on May 02, 2005, as Appl. No. 11/118,768. | ||
| Prior Publication US 2006/0244024 A1, Nov. 02, 2006 | ||
| Int. Cl. H01L 27/108 (2006.01); H01L 29/94 (2006.01) | ||
| U.S. Cl. 257—296 [257/306; 257/307; 257/308; 257/E27.084; 257/E27.085; 257/E27.086] | 23 Claims |
| 1. An integrated circuit comprising:
a plurality of active areas formed in a semiconductor substrate with a substrate surface, each active area having two lateral
sides extending along a first direction with rows of active areas being separated from each other by isolation grooves, wherein
each active area includes a first source/drain region formed adjacent the substrate surface, a second source/drain region
formed adjacent the substrate surface, and a channel region separating the first and second source/drain regions, each of
the first and second source/drain regions being distanced from and oriented with respect to each other along the first direction;
and
gate electrodes disposed along the channel regions and being electrically isolated from the channel regions by gate isolating
layers; and
a plurality of sets of first and second word lines disposed on opposing lateral sides of each of the rows of active areas
and with each of the first and second word lines including a length that extends along the first direction, wherein the first
and second word lines of each set are connected with each other via the gate electrodes of a corresponding row of active areas.
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