forming a patterned gate stack over a substrate that comprises a single crystal semiconductor;

forming a first set of amorphous regions in the substrate using the patterned gate stack as a mask, wherein said first set of amorphous regions comprise n-type source and drain (S/D) extension implants, and wherein said first set of amorphous regions further comprise implanted carbon ions at a first carbon concentration;

forming one or more offset masking structures along sidewalls of the patterned gate stack,

forming a second set of amorphous regions in the substrate using the patterned gate stack and the one or more offset masking structures as masks, wherein said second set of amorphous regions comprise n-type S/D implants, and wherein said second set of amorphous regions further comprise implanted carbon ions at a second, higher carbon concentration; and

annealing the substrate to recrystallize the first and second sets of amorphous regions, thereby forming an n-channel field effect transistor (n-FET) comprising S/D extension regions and S/D regions, wherein the S/D extension regions comprise a first patterned stressor layer comprising a carbon-substituted and tensilely stressed single crystal semiconductor material and having a first substitutional carbon concentration, and wherein the S/D regions comprise a second patterned stressor layer also comprising the carbon-substituted and tensilely stressed single crystal semiconductor material but having a second, higher substitutional carbon concentration.