forming a base layer comprising an electrically conductive element;

forming an upper layer on the base layer, the upper layer forming step comprising forming a third, planarization stop layer over the base layer, a second layer over the third layer, and a first layer over the second layer;

forming an opening through the upper layer to expose a surface of the electrically conductive element and to create a first memory cell subassembly, the opening comprising a first, upper opening segment formed within the first layer, a second opening segment formed within the second layer, and a third opening segment formed within the third layer, the first and second opening segments having first and second widths, the first layer having an overhanging portion extending into the opening so that the first width is shorter than the second width; and

depositing a fill material into the opening to create a second memory cell subassembly comprising a void within the deposited fill material, the void having a width related to the difference between the first and second widths;

etching the second memory cell subassembly anisotropically, thereby forming a sidewall of the fill material in the opening with an electrode hole aligned with the void and exposing the electrically conductive element;

depositing an electrode material into the electrode hole and in contact with the electrically conductive element to create a third memory cell subassembly; and

planarizing the third memory cell subassembly down to the third, planarization stop layer to create a fourth memory cell subassembly having a bottom electrode of the electrode material and a flat top surface defined by the bottom electrode, the dielectric fill material, and the third layer.