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SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR (use of semiconductor devices for measuring G01; resistors in general H01C; magnets, inductors [N: in general], transformers H01F; capacitors in general H01G; electrolytic devices H01G 9/00; batteries, accumulators H01M; waveguides, resonators or lines of the waveguide type H01P; line connectors, current collectors H01R; stimulated emission devices H01S; electromechanical resonators H03H; loudspeakers, microphones, gramophone pick-ups or like acoustic electromechanical transducers H04R; electric light sources in general H05B; printed circuits, hybrid circuits, casings or constructional details of electric apparatus, manufacture of assemblages of electrical components H05K; use of semiconductor devices in circuits having a particular application, see the subclass for the application)
Definition statement
This subclass/group covers:

in general

- discrete and integrated semiconductor devices and

- other electric solid state devices (as far as not provided for in another subclass) and

- details thereof.

This includes the following kind of devices:

- integrated circuit devices, e.g. CMOS integrated devices, DRAM, EPROM, CCD;

- semiconductor devices (e.g. field-effect, bipolar) adapted for rectifying, amplifying, oscillating or switching, e.g. diodes, transistors, thyristors;

- semiconductor devices sensitive to radiation, e.g. photo diodes, photo transistors, solar cells;

- incoherent light emitting diodes, e.g. LED;

- solid state devices using organic materials as the active part or using a combination of organic materials with other materials as the active part, e.g. organic LED or polymer LED;

- electric solid state devices using thermoelectric, superconductive, piezo-electric, electrostrictive, magnetostrictive, galvano-magnetic or bulk negative resistance effects, e.g. thermo couples, Peltier elements, Josephson elements, piezo elements;

- photo-resistors, magnetic field dependent resistors, field effect resistors;

- capacitors with potential-jump barrier, resistors with potential-jump barrier or surface barrier;

- thin-film or thick-film circuits;

- processes and apparatus adapted for the manufacture or treatment of such devices, except where such processes relate to single step processes for which provision exists elsewhere.

Relationship between large subject matter areas

Micro-structural devices or systems are classified in subclass B81B, and the processes and apparatus specially adapted for the manufacture or treatment thereof are classified in subclass B81C. So, by way of example, micro-electro-mechanical devices (MEMS), containing micro-electronic and mechanical components, are classified in group B81B 7/02, and their manufacture, treatment or assembling in the relevant groups of B81C. Micro-structural devices or systems working purely electrically or electronically, or related processes or apparatus for the manufacture or treatment thereof are however not covered by B81B or B81C and are classified in section H, for example in the groups of the current subclass H01L.

Micro-structural devices or systems being of other than purely electrical or electronically type, and apparatus or processes for the manufacture or treatment thereof, which are normally classified in the subclasses B81B and B81C, may be also classified in those groups of H01L providing for their structural or functional features, whenever such features are of interest per se.

Nanostructures, which are normally classified in subclass B82B, may be also classified in those groups of H01L providing for their structural or functional features, whenever such features are of interest per se.

References relevant to classification in this subclass
This subclass/group does not cover:
Micro-mechanical Devices (MEMS)
Processes and apparatus specially adapted for the manufacture or treatment of micro-structural devices or systems
Measurement of Mechanical Vibrations or Ultrasonic, Sonic or Infrasonic Waves
Measurement of Intensity, velocity, Spectral, Content, Polarization, Phase or Pulse Characteristic of Infra-red, Visible or Ultra-Violet Light
Measuring Electrical or Magnetic Variables
Radio Direction-Finding; Radio Navigation; Determining Distance or Velocity by Use of Radio Waves; Locating or Presence-Detecting by Use of the Reflection or Reradiation of Radio Waves;Analogous Arrangements Using Other Waves
Measuring Nuclear or X-Radiation
Electro photography
Systems for Regulating Electrical or Magnetic Variables
Digital Computers
Static Stores
Conductive and Insulating Materials
Resistors in general
Magnets, inductors, transformers
Capacitors in general
Batteries, accumulators
Waveguides, resonators or lines of the waveguide type
Line connectors, current collectors
Stimulated emission devices (e.g. semiconductor laser)
Amplifiers
Electromechanical resonators; impedance networks
Pictorial Communication, e.g. Television
Loudspeakers, microphones, gramophone pick-ups or like acoustic electromechanical transducers
Electric light sources in general
Printed circuits, hybrid circuits, casings or constructional details of electric apparatus, manufacture of assemblages of electrical components
Use of semiconductor devices for measuring
G01
Informative references
Attention is drawn to the following places, which may be of interest for search:
Containers merely intended for transport or storage of wafers except during manufacture or finishing devices thereon
B65D 85/30, B65D85/86
Conveying systems for semiconductor wafers except during manufacture or treatment of semiconductor or electric solid state devices or components thereon
Coating Material
Non-mechanical removal of metallic material from surface
Details of scanning-probe apparatus, in general
Use of semiconductor devices in circuits having a particular application: see particular subclass for the application
Electric discharge tubes or discharge lamps
Special rules of classification within this subclass

In this subclass, documents are classified according to the ECLA Reform approach, i.e. "invention information" is identified with ECLA classification symbols, e.g. H01L 21/26586, while "additional information" is identified with Indexing Code symbols, e.g. H01L 21/26586.

In this subclass, Indexing Codes are mainly attributed with a view to allow retrieval of documents comprising a combination of technical characteristics, some of them being unimportant per se, and, hence, identified with an Indexing Code symbol rather than with the corresponding ECLA symbol.

In this subclass, both the process and apparatus for the manufacture or treatment of a device and the device itself are classified, whenever both of these are described sufficiently to be of interest.

Glossary of terms
In this subclass/group, the following terms (or expressions) are used with the meaning indicated:
Assembly of a Device
The "assembly" of a device is the building up of the device from its component constructional units and includes the provision of fillings in containers.
Complete Device
A "complete device" is a device in its fully assembled state which may or may not require further treatment, e.g. electro-forming, before it is ready for use but which does not require the addition of further structural units.
Component
A "component" is one electric circuit element of a plurality of elements formed in or on a common substrate.
Container
A "container" is an enclosure forming part of the complete device and is essentially a solid construction in which the body of the device is placed, or which is formed around the body without forming an intimate layer thereon.
Device
The term "device" refers to an electric circuit element
Electrodes
"Electrodes" are regions in or on the body of the device (other than the solid state body itself), which exert an influence on the solid state body electrically, whether or not an external electrical connection is made thereto. Electrodes are often referred to as "contacts" in the literature. An electrode may include several portions and the term includes metallic regions which exert influence on the solid state body through an insulating region, (e.g. capacitive coupling) and inductive coupling arrangements to the body. The dielectric region in a capacitive arrangement is regarded as part of the electrode. In arrangements including several portions only those portions which exert an influence on the solid state body by virtue of their shape, size or disposition or the material of which they are formed are considered to be part of the electrode. The other portions are considered to be "arrangements for conducting electric current to or from the solid state body" or "interconnections between solid state components formed in or on a common substrate",, e.g. interconnections.
Encapsulation
An "encapsulation" is an enclosure which consists of one or more layers formed on the body and in intimate contact therewith.
Integrated Circuit
An "integrated circuit" is a device where all components, e.g. diodes, resistors, are built up on a common substrate and form the device including interconnections between the components.
Integration Process
Processes for the manufacture of at least two different components where the process is especially adapted to their integration, e.g. to take advantage of the integration or to reduce their manufacturing cost. Example: in a CMOS process, the same ion implant dopes the p-MOS gate and the n-MOS source and drain. Consequently, a process for the manufacture of a component per se is not considered as an integration process, even though that component will be part of an integrated circuit.
Interconnection
Refers to the arrangement of conductive and insulating regions aimed at electrically connecting the respective electrodes of at least two device units, e.g. two transistors.
Parts
The term "parts" includes all structural units which are included in a complete "device".
Solid State Body
The expression "solid state body" refers to the body of material within which, or at the surface of which, the physical effects characteristic of the device occur. In thermoelectric devices it includes all materials in the current path.
Wafer
A "wafer" means a slice of semiconductor or crystalline substrate material, which can be modified by impurity diffusion (doping), ion implantation or epitaxy, and whose active surface can be processed into arrays of discrete devices or integrated circuits.
Synonyms and Keywords

In patent documents the expression "package" is often used with the meaning "container" and "encapsulation".

Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof ([N: multistep manufacturing processes for passive two-terminal components without a potential-jump or surface barrier for integrated circuits H01L 28/00;] (processes or apparatus peculiar to the manufacture or treatment of devices provided for in groups H01L 31/00 to H01L 51/00 or of parts thereof, see these groups; single-step processes covered by other subclasses, see the relevant subclasses, e.g. C23C, C30B; photomechanical production of textured or patterned surfaces, materials or originals therefor, apparatus specially adapted therefor, in general G03F
Definition statement
This subclass/group covers:

Processes and apparatus that are specially adapted for the manufacturing of semiconductor or solid state devices belonging to the type:

  • Integrated circuit devices, e.g. CMOS integrated devices, DRAM, EPROM, CCD;
  • Semiconductor devices (e.g. field-effect, bipolar) adapted for rectifying, amplifying, oscillating or switching, e.g. diodes, transistors, thyristors;

This main group includes;

- Manufacture or treatment of the above semiconductor devices or of parts thereof

- Manufacture or treatment of solid state devices other than semiconductor devices, or of parts thereof

- Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

- Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; manufacture of integrated circuit devices or of parts thereof

References relevant to classification in this main group
This subclass/group does not cover:
Processes or apparatus specially adapted for the manufacture or treatment of devices provided for in groups H01L 31/00-H01L 51/00 or of parts thereof, see these groups
Informative references
Attention is drawn to the following places, which may be of interest for search:
Processes for applying liquids or other fluent materials
Liquid cleaning (in general)
Machines, Devices, or Processes for Grinding or Polishing
Containers, packaging elements or packages specially adapted for particular articles or materials
Shaped ceramic Products
Polishing compositions
Cleaning Compositions
Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating (CVD)
Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds,without leaving reaction products of surface material in the coating
Etching metallic material by chemical means
Processes for the Electrolytic or Electrophoretic Production of Coatings
Single Crystal Growth; Epitaxy
Testing individual semiconductor devices
Preparation of originals for the photomechanical production of textured or patterned surfaces
Photolithographic, production of textured or patterned surfaces
Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces
Discharge tubes with provision for introducing objects or material to be exposed to the discharge (plasma etching; ion implantation)
Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
Special rules of classification within this main group

Single mono-steps for which a provision exists elsewhere in ECLA need not to be classified in H01L 21/00, except if they are specific to the fabrication of semiconductor devices as defined under H01L 21/00. E.g., apparatuses which are not specific to the fabrication of these devices, e.g. apparatuses for depositing layers, are classified in C23C or C30B.

Multi-aspect classification is used for subject matter characterized by several aspects, for example, a process and its particular use. Single steps forming part of a multi step process should also be classified when they present a special interest or particular features.

Indexing Codes under ECLA reform are used.

Direct pre-treatment or direct post-treatment of a specific step is classified under the specific step if no other place exists in H01L 21/00. Example: annealing after layer coating is classified together with the coating. Exception: cleaning, see H01L 21/02041

In H01L 21/00, poly-silicon is generally considered as a conductive material for classification purposes, except for its deposition (H01L 21/02365) where it is considered as semiconducting.

Polishing or chemical-mechanical polishing are not distinguished for classification.

Machines and apparatuses for which a provision exists somewhere else in ECLA are not classified In H01L 21/00. For example apparatus for deposition of materials are classified in C23C or C30B.

Machines and apparatuses for which no particular provision exists in ECLA are classified in H01L 21/67 and subgroups. See also the notes under H01L 21/67.

Simple and direct use of a machine (for example plasma machine, polishing machine etc.) need not to be classified in H01L 21/00.

Subject matter relating to processes and apparatus which are clearly suitable for manufacture or treatment of devices whose bodies comprise elements of the fourth group of the Periodic System (silicon, germanium), and where the material used is not explicitly specified, is classified in the subgroups relating to semiconductors of the fourth group of the Periodic System (silicon, germanium).

For multistep processes, a junction between two regions of the same material but in a different crystalline state, e.g. amorphous silicon or polysilicon emitters on single crystalline silicon, is not considered as a heterojunction.

Glossary of terms
In this subclass/group, the following terms (or expressions) are used with the meaning indicated:
Dry Process
refers to processes wherein only gases or vapours are provided on the surface of a substrate, e.g. a wafer, irrespective of the physical state of the reaction products, gaseous, liquid or solid.
Wet Process
refers to processes wherein only liquids are provided at the surface of a wafer, including the condensation on the surface of a wafer of gaseous components.
Pre-, post-treatment
direct, for example in situ, treatment, preceding or following a main technological step, aimed at improving said main technological step or its result. Not considered as a technological step per se.Examples: - annealing after implant or deposition, including crystallization, - cleaning before or after a technological step, - modifying an insulating layer just after its formation, e.g. implantation after deposition
After treatment
Subsequent main technological step.Examples: - patterning or polishing of a layer after deposition- modifying an insulating layer after a step which is not the formation of the insulating layer
Synonyms and Keywords

In patent documents the following abbreviations are often used:

CVD
Chemical vapour deposition
PECVD
Plasma enhanced CVD
LPCVD
Low pressure CVD
PVD
Physical Vapour Deposition
ALD
Atomic layer deposition
ALE
Atomic layer epitaxy
CMP
Chemical mechanical polishing
ECMP
Electrochemical CMP
SOI
Silicon on Insulator
BESOI
Bonded and Etched-Back Silicon-On-Insulator
SOS
Silicon on Sapphire
HSG
Hemispherical grain
RIE
Reactive ion etching
BSG
boron silicate glass
PSG
phosphorous silicate glass
BPSG
boron phosphorous silicate glass
USG
Undoped silicate glass
FSG
Fluorine silicate glass
PZT
Lead zirconate titanate
BST
Barium strontium titanate
HSQ
Hydrogen silsesquioxane
MBE
Molecular beam epitaxy
ELO
Epitaxial lateral overgrowth
MIS
Metal-insulator-semiconductor
MOS
Metal-oxide-semiconductor
CMOS
Complementary MOS
DMOS
Double diffused MOS
VDMOS
Vertical DMOS
LDMOS
Lateral DMOS
IMPATT
Impact Ionization Avalanche Transit Time
TRAPATT
Trapped Plasma Avalanche Triggered Transistor
SITh
Static induction thyristor
FCTh
Field controlled thyristor
IGBT
Insulated Gate Bipolar Transistor
HET
Hot electron transistor
SET
Single electron transistor
SIT
Static Induction Transistor
MBT
Metal base transistor
RHET
Resonant tunnelling hot electron transistor
RTT
Resonant tunnelling transistor
BBT
Bulk barrier transistor
PBT
Permeable Base Transistor
HFET
Heterostructure FET
HIGFET
Heterostructure Insulated Gate FET
SISFET
Semiconductor-insulator-semiconductor FET
HJFET
Hetero Junction FET
MISFET
Metal-insulator-semiconductor FET
JFET
Junction FET
FinFET
FET with Fin-type channel
MuGFET
Multi Gate FET
HEMT
High Electron Mobility Transistor
PDBT
Planar doped barrier transistor
CHINT
Charge injection transistor
LDD
lightly doped drain
DDD
Double diffused drain
EPIC
Epitaxial Passivated Integrated Circuit
LOCOS
Local Oxidation of Silicon
SWAMI
Side Wall Masked Isolation
SILO
Sealed Isolation LOCOS
SIMOX
Separation by Implantation of Oxygen
FIPOS
Full Isolation by porous oxidized silicon
ELTRAN
Epitaxial Layer Transfer
SEG
Selective Epitaxial Growth
DRAM
Dynamic RAM
CCD
Charge Coupled Device
[N: Preparing wafers]
Definition statement
This subclass/group covers:

Multi-step processes for the manufacture of semiconductor wafers for the fabrication of semiconductor devices as defined under H01L 21/00, prior to the fabrication of any device or part of device, i.e. between the sawing of ingots (covered by B28D) and the cleaning of the wafers (H01L 21/02041), e.g. grinding followed by lapping and polishing.

Covers the preparation of bulk semiconductor wafers (e.g. bulk silicon wafers).

Relationship between large subject matter areas

See also H10L21/8258, which has been used for classifying the fabrication of substrates containing parts of Group-IV and Group AIII-BV semiconductors.

See also C30B 33/00.

References relevant to classification in this group
This subclass/group does not cover:
The fabrication of inhomogeneous wafers, like SOI
The fabrication of wafers comprising portions of different materials
Thermal smoothening
Marking of wafers
Forming flats
Special rules of classification within this group

Multiple classification on different aspects is made, provided the invention is sufficiently disclosed on these different aspects.

Wafers per se are classified in H01L 29/06

[N: Preparing bulk and homogeneous wafers]
Definition statement
This subclass/group covers:

Bulk, homogeneous wafers:

- Group IV, Si, Ge,

- Group III-V, GaAs, InP,

[N: Specific process step]
Definition statement
This subclass/group covers:

Multistep process for preparing wafers where the accent is put on a specific step.

[N: Grinding, lapping]
Definition statement
This subclass/group covers:

Multistep process for preparing wafers where the accent is put on the grinding or lapping, e.g. multiple grinding steps.

[N: Backside treatment]
Definition statement
This subclass/group covers:

Multistep process for preparing wafers where the accent is put on the backside treatment.

Includes backside treatment for recognition purposes

[N: Chemical etching]
Definition statement
This subclass/group covers:

Multistep process for preparing wafers where the accent is put on the chemical etching step or steps.

Informative references
Attention is drawn to the following places, which may be of interest for search:
Chemical or electrical treatment, e.g. electrolytic etching
[N: Edge treatment, chamfering]
Definition statement
This subclass/group covers:

Multistep process for preparing wafers where the accent is put on the edge treatment, e.g. chamfering.

References relevant to classification in this group
This subclass/group does not cover:
Does not cover the processing of edges of Smart Cut donor substrates, classified in reclaiming/reprocessing
[N: Mirror polishing]
Definition statement
This subclass/group covers:

Multistep process for preparing wafers where the accent is put on the mirror polishing.

Special rules of classification within this group

In case a mechanical mirror polishing is completed by a chemical flattening step, e.g. a gaseous flattening step, the latter is classified independently.

[N: Setting crystal orientation]
Definition statement
This subclass/group covers:

Multistep processes for preparing wafers having a specific orientation planes as useful plane, or a specific orientation plane in a plane parallel to the surface.

Informative references
Attention is drawn to the following places, which may be of interest for search:
Single-crystal growth by pulling from a melt characterised by the seed, e.g. its crystallographic orientation
[N: Making porous regions on the surface]
Definition statement
This subclass/group covers:

Making a surface of the wafer porous. Includes formation of internal porous regions.

References relevant to classification in this group
This subclass/group does not cover:
Localized formation (using e.g. masks) of porous regions
[N: by reclaiming or re-processing]
Definition statement
This subclass/group covers:

Multistep processes for reclaiming or re-processing, a wafer containing more than a cleaning process. Also contains the re-processing of Smart-Cut donor substrates.

Informative references
Attention is drawn to the following places, which may be of interest for search:
Specific cleaning for reclaiming or reprocessing
[N: Shaping]
Definition statement
This subclass/group covers:

Processes adapted to change the shape of a wafer, either in the surface plane (e.g. square, rectangular wafers), or in cross section (bone cross section).

References relevant to classification in this group
This subclass/group does not cover:
The provision of flats, classified with the fabrication of the ingot
[N: Preparing wafers having an insulating layer, e.g. SOI wafers]
Special rules of classification within this group

This group is not used for classification. Subject matter relating to SOI is covered by H01L 21/762.

[N: Cleaning]
Definition statement
This subclass/group covers:

Cleaning of wafers before or during manufacturing;

Cleaning is the removal of entities which were always unwanted, like particles, impurities, stringers, fences etc. Also includes the removal of edge beads or unwanted coatings on edges or backside of the wafers etc., except photoresist edge beads and photoresist on backside.

Removal of entities which have had a use or a function (sidewalls, resists etc.) is not considered to be a cleaning.

Includes the removal of natural oxide, see also the section "Special rules for classification within this group" below.

Starts with the deep cleaning carried out before first fabrication step (Piranha-RCA) up to cleaning after singulation.

Relationship between large subject matter areas

Rinsing and drying are seen as a post-treatment of a wet cleaning, classified together with wet cleaning in H01L 21/02052.

References relevant to classification in this group
This subclass/group does not cover:
Processes for the removal of only photoresists, classified in
Removal of excess metal after silicidation, classified in
Does not cover processes for the removal of photoresists edge beads after coating
Does not cover the transformation of an impurity or contaminant in something else remaining on the device, e.g. passivation, classified with passivation in general
Informative references
Attention is drawn to the following places, which may be of interest for search:
Cleaning by methods involving the use of tools, brushes, or analogous members, the use or presence of liquid or steam, the use of air flow or gas flow; Cleaning by electrostatic means
Detergent compositions, e.g. cleaning solutions or liquids
Cleaning apparatus
Special rules of classification within this group

Multiaspect classification is used in H01L 21/02041 and subgroups.

Removal of only natural oxide is also classified in H01L 21/311 if the process is of special relevance for thick oxides.

Removal of impurities, e.g. side walls after RIE, together with the photoresist is classified in H01L 21/02041, and additionally in H01L 21/311, if the resist removal method is peculiar.

Synonyms and Keywords

In patent documents the following abbreviations are often used:

RCA
standard clean composed of SC-1 and SC-2 at least, with piranha and HF or DHF
SC-1
standard clean 1: NH4OH-H2O2
SC-2
standard clean 2: HCl, H2O2
DHF
diluted HF
Piranha
H2SO4-peroxide
[N: Cleaning before device manufacture, i.e. Begin-Of-Line process]
Definition statement
This subclass/group covers:

Cleaning of the wafer before any manufacturing step for the device is carried out.

Informative references
Attention is drawn to the following places, which may be of interest for search:
Processes for the removal of only photoresist
Removal of excess metal after silicidation
Does not cover processes for the removal of photoresist edge beads after coating
Does not cover the transformation of an impurity or contaminant in something else remaining on the device, e.g. passivation
[N: Dry cleaning only (H01L 21/02085 takes precedence)]
Definition statement
This subclass/group covers:

All cleaning steps are dry, or when the invention is focussed on a dry cleaning aspect, the cleaning also containing more classical wet steps, like RCA.

References relevant to classification in this group
This subclass/group does not cover:
Cleaning of diamond
[N: Wet cleaning only (H01L 21/02085 takes precedence)]
Definition statement
This subclass/group covers:

Wet cleaning.

References relevant to classification in this group
This subclass/group does not cover:
Cleaning of diamond
Special rules of classification within this group

Rinsing and drying are seen as a post-treatment of a wet cleaning, classified together with wet cleaning in H01L 21/02052.

[N: combining dry and wet cleaning steps (H01L 21/02085 takes precedence)]
Definition statement
This subclass/group covers:

The sequence of combining wet and dry steps.

References relevant to classification in this group
This subclass/group does not cover:
Cleaning of diamond
Special rules of classification within this group

Rinsing and drying are seen as a post-treatment of a wet cleaning, classified together wet cleaning in H01L 21/02052.

[N: Cleaning during device manufacture]
Definition statement
This subclass/group covers:

Cleaning when at least a fabrication step for a device (for example, first oxidation) has been carried out.

[N: during, before or after processing of insulating layers]
Definition statement
This subclass/group covers:
  • Cleaning after etching gate sidewalls and etching of gate oxide.
  • Cleaning after formation of a resist pattern
[N: Cleaning for reclaiming]
Definition statement
This subclass/group covers:

Reclaiming of semiconductor wafers as well as donor semiconductor wafers, e.g. donors in Smart-Cut®

References relevant to classification in this group
This subclass/group does not cover:
Etching for reclaiming
[N: product to be cleaned]
Definition statement
This subclass/group covers:

Special products to be cleaned, including particular materials as well as substrates comprising particular features, like vertical features, isolated sidewalls, etc.

[N: Cleaning of wafer edges]
Definition statement
This subclass/group covers:

Removal of edge beads.

References relevant to classification in this group
This subclass/group does not cover:
Removal of photoresist edge beads
[N: Cleaning of wafer backside]
Definition statement
This subclass/group covers:

Removal of impurities or unwanted materials on backside, including parasitic coatings.

References relevant to classification in this group
This subclass/group does not cover:
Removal of photoresist edge beads
[N: only mechanical cleaning]
Definition statement
This subclass/group covers:

The group covers inventions wherein the mechanical aspect is of particular importance. Does not exclude some enhancement by chemical means.

[N: only involving lasers, e.g. laser ablation]
Definition statement
This subclass/group covers:

Covers processes wherein the laser action has a primary function, with or without chemical, mechanical or electrical assistance.

Informative references
Attention is drawn to the following places, which may be of interest for search:
Cleaning using a laser per se
[N: only involving supercritical fluids]
Definition statement
This subclass/group covers:

Covers processes wherein the supercritical fluid has a primary function, with or without chemical, mechanical or electrical assistance.

[N: Forming layers (deposition in general C23C; crystal growth in general C30B)]
Definition statement
This subclass/group covers:

Processes for the formation of inorganic and organic layers on a substrate, except photoresist layers (see H01L 21/027), for the fabrication of semiconductor devices as defined under H01L 21/00.

In situ pre- and post-treatments of these processes.

Processes for the formation of a multiplicity of these layers.

Relationship between large subject matter areas

Processes for coating materials in general: C23C

Processes for the electrolytic coating of materials in general: C25D

Processes for the single-crystal growth of materials in general: C30B

References relevant to classification in this group
This subclass/group does not cover:
Processes for forming photoresist layers, covered in
Processes for forming conductive layers, covered by
Informative references
Attention is drawn to the following places, which may be of interest for search:
Groups and their subdivisions for general aspects of formation of layers.
Photoresist per se
Special rules of classification within this group

- Multiple classification is possible for different aspects, provided the invention is sufficiently disclosed on these different aspects.

- Multistep processes for fabricating laminates of insulating and conductive layers, for example insulated gates or capacitors, are classified in the corresponding application, H01L 21/28 for the insulated gates, H01L21/02B3 for the capacitors etc. and do not need to be systematically classified in H01L 21/02107. However a group symbol in H01L 21/02107 may be given in case the process for forming the insulating layer is considered of general interest.

Glossary of terms
In this subclass/group, the following terms (or expressions) are used with the meaning indicated:
ALD
atomic layer deposition
ALE
atomic layer epitaxy
MBE
molecular beam epitaxy
PECVD
plasma enhanced chemical vapour deposition
PVD
physical vapour deposition
CVD
chemical vapour deposition
[N: Forming insulating materials on a substrate]
Definition statement
This subclass/group covers:

Processes for the formation of inorganic and organic insulating layers on a substrate, except photoresist layers (see H01L 21/027), for the fabrication of semiconductor devices as defined under H01L 21/00.

In situ pre- and post-treatments of these processes.

Processes for the formation of a multiplicity of these layers.

Includes fabrication of insulating

- porous layers,

- organic layers, like polyimide, cyclobutenes etc.

- Spin On Glass layers,

- silicate layers,

- inorganic layers, like SiO2, Si3N4, Al2O3, high-k layers, perovskites etc.

Relationship between large subject matter areas

Processes for coating materials in general, including insulating materials: C23C

Processes for the electrolytic coating of materials in general: C25D

Organic or polymer layer composition: see C08G

References relevant to classification in this group
This subclass/group does not cover:
Processes for forming photoresist layers
Informative references
Attention is drawn to the following places, which may be of interest for search:
Photoresist per se
Special rules of classification within this group

Multiple classification is made for different aspects (type of layer, formation process, treatment of layer), provided the invention is sufficiently disclosed on this aspect.

The process must be adapted or specific to the fabrication of semiconductor devices as defined under H01L 21/00. The mere mentioning of an intended use in semiconductor fabrication does not require that the document being given a group symbol in H01L 21/02107.

If the deposition is specifically adapted to a specific application, with details as to this specific application, e.g. the fabrication of a MIS or MOS electrode or interconnections, the document should additionally be classified in this specific application, for example in H01L 21/28 for the MIS or MOS aspect.

[N: characterised by the material of the layer]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Layers comprising sub-layers, i.e. multi-layers, are additionally classified in
Porous layers are additionally classified in
[N: the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon]
References relevant to classification in this group
This subclass/group does not cover:
Carbon Nitride.
H10L21/02K2C1J
[N: carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC (polymers per se C08G, photoresist per se G03F)]
Definition statement
This subclass/group covers:

Carbon Nitride.

Carbon based polymeric material

[N: the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Halogen doped silicon oxides, e.g. fluorine, containing BPSG, PSG, BSG
Special rules of classification within this group

Halogen containing materials, e.g. fluorine, containing BPSG, PSG, BSG, are additionally classified in H01L 21/02131

[N: the material being a silicon oxide, e.g. SiO2]
Definition statement
This subclass/group covers:

The formation of silicon oxide layers is classified in this group regardless of the precursor or of the process of formation.

Informative references
Attention is drawn to the following places, which may be of interest for search:
In case of explicit statements on doping, on rest-groups, or on material components, see
Deposition of silicon oxide from organic precursors without further statements on film composition is classified here and in
[N: the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides (H01L 21/02126 and H01L 21/0214 take precedence)]
References relevant to classification in this group
This subclass/group does not cover:
The formation of material containing Si, O and C, with or without additional elements
The formation of material containing Si, O and N, with or without additional elements
[N: the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz (H01L 21/02126 and H01L 21/0214 take precedence)]
References relevant to classification in this group
This subclass/group does not cover:
The formation of material containing Si, N and C, with or without additional elements
The formation of material containing Si, O and N, with or without additional elements
[N: the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides (materials containing silicon H01L 21/02123; metal silicates H01L 21/02142)]
References relevant to classification in this group
This subclass/group does not cover:
Materials containing silicon
Metal silicates
[N: characterised by the metal (H01L 21/02197 takes precedence)]
References relevant to classification in this group
This subclass/group does not cover:
Materials having a perovskite structure, e.g. BaTiO3
H10L21/02K2C1M5
[N: the material having a perovskite structure, e.g. BaTiO3]
Special rules of classification within this group

Perovskites are not classified in H01L 21/02175 and subgroups thereof.

[N: the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides (adhesion layers or buffer layers H01L 21/02304, H01L 21/02362)]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Adhesion or buffer layers
[N: the compound comprising silicon and oxygen]
References relevant to classification in this group
This subclass/group does not cover:
Mixtures of silane and oxygen
[N: the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane]
Glossary of terms
In this subclass/group, the following terms (or expressions) are used with the meaning indicated:

In this group, the following terms or expressions are used with the meaning indicated:

Alkoxysilane
siloxane
[N: the compound comprising silicon and nitrogen]
References relevant to classification in this group
This subclass/group does not cover:
Mixtures of silane and oxygen
[N: formation by a process other than a deposition process]
Special rules of classification within this group

Subject matter classified in the range H01L 21/0223 to H01L 21/02249 is additionally classified in H01L 21/02252, H01L 21/02255, and H01L 21/02258 depending on the type of reaction.

[N: formation by plasma treatment, e.g. plasma oxidation of the substrate (after treatment of an insulating film by plasma H01L 21/3105 and subgroups)]
References relevant to classification in this group
This subclass/group does not cover:
After treatment of an insulating film by plasma
Informative references
Attention is drawn to the following places, which may be of interest for search:
Formation of an insulating film by introduction of substances into an already existing insulating film is covered by
[N: formation by thermal treatment (H01L 21/02252 takes precedence; after treatment of an insulating film H01L 21/3105 and subgroups)]
References relevant to classification in this group
This subclass/group does not cover:
Formation of insulating layers by plasma treatment, e.g. plasma oxidation of the substrate
After treatment of an insulating film by plasma
[N: deposition from the gas or vapour phase]
Definition statement
This subclass/group covers:

Deposition methods in which the gas or vapour is produced by physical means, e.g. ablation from targets or heating of source materials.

[N: deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition]
Definition statement
This subclass/group covers:

Deposition methods in which the gas or vapour is produced by physical means, i.e. by ablation from targets.

[N: deposition by thermal evaporation, H01L 21/02293 takes precedence]
Definition statement
This subclass/group covers:

- Deposition methods in which the gas or vapour is produced by heating of source materials.

- Molecular beam epitaxy

Informative references
Attention is drawn to the following places, which may be of interest for search:
Formation of epitaxial insulating films by a deposition method also under
[N: deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (H01L 21/02266 takes precedence)]
References relevant to classification in this group
This subclass/group does not cover:
Deposition by physical ablation of a target, like sputtering, reactive sputtering, physical vapour deposition, pulsed laser deposition
[N: deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Deposition by decomposition or reaction of gaseous or vapour phase compounds in the presence of a plasma (PECVD)
Special rules of classification within this group

Subject matter relating to cyclic plasma CVD is additionally classified in H01L 21/02274

[N: printing, e.g. ink-jet printing (per se B41J)]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Printing in general
[N: formation of epitaxial layers by a deposition process (epitaxial growth per se C30B)]
References relevant to classification in this group
This subclass/group does not cover:
Formation of non-epitaxial layers by MBE
Atomic layer epitaxy [ALE]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Epitaxial growth in general
[N: characterised by the treatment performed before or after the formation of the layer (H01L 21/02227 and subgroups take precedence)]
Definition statement
This subclass/group covers:

Treatments, carried out just before or just after the formation of an insulating layer, which do not participate in the formation of the layer itself, but which are directly linked to the layer formation.

References relevant to classification in this group
This subclass/group does not cover:
Processes participating to the formation of a layer, for example oxidation or nitridation of silicon to form an oxide or nitride layer
After treatments like - etching - cleaning - planarising
Special rules of classification within this group

Pre- or post treatments of general nature (pre-, post-cleaning, pre-, post conditioning etc.) without details or routine annealing steps, i.e. thermal treatment without further features as to a special atmosphere, presence of a plasma, thermally induced chemical reactions, change of phase or crystal structure, need not to be given this group symbol.

[N: pre-treatment]
Definition statement
This subclass/group covers:

- Treatments to improve adhesion or change the surface termination

References relevant to classification in this group
This subclass/group does not cover:
Treatments by etching
[N: in-situ cleaning]
References relevant to classification in this group
This subclass/group does not cover:
Ex situ cleaning, covered by
[N: after-treatment]
Definition statement
This subclass/group covers:

The definition should read "post-treatment" instead of after-treatment.

Only covers processes that are part of the layer formation.

References relevant to classification in this group
This subclass/group does not cover:
After- treatments performed after completion of the insulating layer
Special rules of classification within this group

Functionalization just after formation should be classified here.

In case the process would also be of interest as an after treatment (H01L 21/3105), both classes should be given.

[N: introduction of substances into an already existing insulating layer; H01L 21/02227 and subgroups take precedence]
Definition statement
This subclass/group covers:

Processes for introducing substances into the formed insulating layer e.g. introduction of phosphorus into silicon oxide, or introduction of nitrogen into silicon nitride to change stoichiometry.

Informative references
Attention is drawn to the following places, which may be of interest for search:
For the method of introduction of the dopant
Special rules of classification within this group

Introduction of substances into the formed insulating layer is classified both here and in H01L 21/3115

[N: into a nitride layer, e.g. changing SiN to SiON]
Definition statement
This subclass/group covers:

Oxidation of silicon nitride to form silicon oxynitride.

[N: into an oxide layer, e.g. changing SiO to SiON]
Definition statement
This subclass/group covers:

Nitridation of silicon oxide to form silicon oxynitride.

[N: in-situ cleaning after layer formation, e.g. removing process residues (cleaning compositions per se C30D; cleaning in general B08B)]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Cleaning in general
Cleaning compositions in general
Subject matter relating to cleaning processes for semiconductor device fabrication
[N: Forming inorganic semiconducting materials on a substrate (for light-sensitive devices H01L 31/00)]
Definition statement
This subclass/group covers:

Processes for the formation of inorganic semiconductors on a substrate.

Processes for forming doped inorganic semiconductors.

In situ pre-and post-treatments of inorganic semiconductor materials.

Processes for the formation of multiple layers of inorganic semiconductors, comprising heterostructures.

The formed semiconductor layer may be crystalline (mono-, poly-, micro-crystalline) or amorphous.

Relationship between large subject matter areas

Attention is drawn to the groups C23C, C25D, C30B and their subdivisions for general aspects of these techniques.

References relevant to classification in this group
This subclass/group does not cover:
Processes for forming layers only characterized by the purely chemical aspects of the used precursors
Nanosized carbon materials, e.g. fullerenes, carbon nanotubes
Informative references
Attention is drawn to the following places, which may be of interest for search:
Formation of inorganic semiconductors for light
H10L31/00
Processes specially adapted for the manufacture or treatment of organic semiconductor or solid state devices or of parts thereof
Fullerenes used in semiconductor or solid state devices
Special rules of classification within this group

- Multi-aspect classification is possible in

- substrates

- intermediate layers,

- deposited layers,

- formation type,

provided the invention is sufficiently disclosed on these different aspects.

- Processes characterized by the chemical aspects of the used precursors are not classified under H01L 21/02365, but are given an Indexing Code.

- Processes for forming semiconductor layers specific to devices as defined under H01L 31/00 or H01L 33/00 may be classified, provided the invention is sufficiently disclosed on the aspect of forming the semiconductor layers, and the material may be used for devices as defined in H01L 21/00.

- A material is classified in the corresponding group when an emphasis has been put on said material, for example with an example.

- Long lists of materials do not require a classification for each material.

- In case the composition of a material may be covered by two or more groups, the document should be classified in each concerned group. For example, CdSSe should be classified in sulphide of II-VI and selenide of II-VI semiconductors.

Fullerenes and carbon nanotubes are considered to be organic materials.

[N: Nanotubes (carbon nanotubes H01L 51/0048)]
References relevant to classification in this group
This subclass/group does not cover:
Carbon nanotubes used in semiconductor or solid state devices
[N: Pretreatments (cleaning in general H01L 21/02041)]
References relevant to classification in this group
This subclass/group does not cover:
Ex situ cleaning
[N: After-treatments (planarisation in general H01L 21/304)]
References relevant to classification in this group
This subclass/group does not cover:
After-treatments for improving the planarity of the layers, e.g. thermal smoothening of layers
[N: Forming conducting materials on a substrate]
Special rules of classification within this group

This group is not used for classification; subject matter relating to the formation of conductive material on a semiconductor substrate is classified in H01L 21/283 to H01L 21/288, 3205 and H01L 21/768.

Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L 21/18 or H01L 21/34 [N: (photographic masks or originals per se G03F 1/00; registration or positioning of photographic masks or originals G03F 9/00; photographic cameras G03B; control of position G05D 3/00)]
Definition statement
This subclass/group covers:

Formation of masks to be used for etching or patterning, formed out of a layer formed or deposited on the wafer. Includes inorganic masks (metallic or insulating materials) as well as organic masks.

Relationship between large subject matter areas

Composition of photosensitive polymers, see G03F 7/00.

Photographic masks of the stencil tape or originals per se: G03F 1/00

Registration or positioning of photographic masks or originals: G03F 9/00

Photographic cameras G03B

Control of position G05D 3/00

References relevant to classification in this group
This subclass/group does not cover:
Masks per se, e.g. free standing mask, stencil mask
Formation of photoresist masks per se
Formation and use of stencil masks
Formation of masks for non patterning purposes:
masks for implantation
masks for forming insulating layers
masks for selective growth
H01L21/02K4S3E3
Informative references
Attention is drawn to the following places, which may be of interest for search:
Photographic masks or originals per se
Registration or positioning of photographic masks or originals
Photographic cameras
Control of position
Special rules of classification within this group

In main group H01L 21/00 and subgroup thereof, a mask is defined as a layer, which is coated directly onto the surface of the wafer.

A free standing mask (stencil mask) laid on the wafer is not considered as a mask in the sense of H01L 21/00.

Masks are classified in H01L 21/00 only under the condition that its treatment or structure has been specially adapted to the fabrication of a device covered by H01L 21/00. Examples are:

- masks used for more than one technological step during device fabrication,

- masks whose structure, formation or treatment are adapted to the nature of the layers or materials used in the fabrication of semiconductor device, or to the device itself

[N: comprising organic layers]
Definition statement
This subclass/group covers:

Covers polymeric masks, including photo-sensitive masks (photoresist) as well as non photo-sensitive masks, e.g., wax, polyimide etc.

[N: characterised by the treatment of photoresist layers]
Definition statement
This subclass/group covers:

Treatment of photoresist layers peculiar to fabrication of electronic devices.

H01L 21/0273 covers the treatment of photoresist which is not peculiar to the type of resist (UV, e-beam, ion beam resist), for example:

- method of reflowing the resist,

- method of hardening the resist

Informative references
Attention is drawn to the following places, which may be of interest for search:
Photoresists and processing of photoresists in general
Special rules of classification within this group

- If the treatment is peculiar to the resist type (light, e-beam or ion-beam resist), then it is classified in the corresponding subgroup. If not, remains in H01L 21/0273.

- Chemical amplification is considered to be peculiar to the resist type.

- fabricating masks by irradiating a resist with different types of radiation, e.g. photons and electrons, the document is classified in H01L 21/0273.

[N: using an anti-reflective coating (anti-reflective coating for lithography in general G03F 7/09)]
Definition statement
This subclass/group covers:

Anti-reflective coatings specially adapted for devices as defined under H01L 21/00.

Covers organic as well as inorganic anti-reflective coatings

Informative references
Attention is drawn to the following places, which may be of interest for search:
Antireflective coatings for lithography in general
[N: Electrolithographic processes]
Definition statement
This subclass/group covers:

Multilayer structures and special structures adapted to evacuate charges, e.g. multilayer resists with a conductive layer.

Special rules of classification within this group

Multilayer resists for electrolithography should additionally be classified in G03F 7/00.

[N: Röntgenlithographic or X-ray lithographic processes]
Definition statement
This subclass/group covers:

Includes multilayer structures.

Special rules of classification within this group

Multilayer resists for Röntgenlithography should additionally be classified in G03F 7/00

comprising inorganic layers
Definition statement
This subclass/group covers:

Processes for forming masks comprising inorganic layers.

Special rules of classification within this group

This group H01L 21/033 acts as a head group for inorganic masks for patterning layers. Multiple classification with H01L 21/31144 (masks for etching insulating layers), H01L 21/32139 (masks for etching conductive layers and polysilicon layers) and H01L 21/308 (masks for etching semiconductors) is possible.

[N: for lift-off processes]
Definition statement
This subclass/group covers:

Processes for forming masks to be used for lifting off another layer (for example having a multilayer structure or special profile) irrespective of their fabrication process

Example:

EP2132770

References relevant to classification in this group
This subclass/group does not cover:
Lifting off for obtaining the mask
[N: characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane]
References relevant to classification in this group
This subclass/group does not cover:
Masks having an orientation or shape adapted to the requirements of an orientation dependent etching
H10L21/308D
[N: characterised by their behaviour during the process, e.g. soluble masks, redeposited masks]
Definition statement
This subclass/group covers:

Mask having a shape being directly affected by and during the patterning process, e.g. erosion or re-deposition, such that the shape of the mask changes during the patterning process.

[N: characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment]
Definition statement
This subclass/group covers:

Processes for forming masks involving special processes, like lift-off, or sidewall formation, e.g. deposition on a step followed by anisotropic etching, or to modify the mask, e.g. oxidation of an Aluminium layer, hardening, before etching step.

[N: Process specially adapted to improve the resolution of the mask]
Definition statement
This subclass/group covers:

Process specially adapted to provide a mask below the lithographic resolution limit.

Special rules of classification within this group

Sidewall masks may also be classified in H01L 21/0337. As a sidewall spacer has inherently a sub lithographic size, it does not require an automatic group symbol here.

the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
Definition statement
This subclass/group covers:

The group range from H01L 21/04 to H01L 21/326 covers processes for fabrication of semiconductor devices on substrates belonging to the semiconductors of

- group IV: Si, Ge,

- group IV: carbon, diamond,

- group III-V: GaAs, GaN, InP etc.

- group IV-IV: Silicon Carbide,

- inorganic semiconductors other than the above mentioned materials, e.g. II-VI semiconductors,

- bonding or joining semiconductor bodies

- diffusion, and alloying of impurities in these semiconductor materials

- bombardment of these semiconductor materials with radiation,

- Manufacture of electrodes on these semiconductor materials,

- special treatments of these semiconductor materials, like

thermal treatments, e.g. gettering

electroforming

mechanical treatments of these semiconductor materials

hydrogenation of these materials

treatments of insulating layers formed on these materials, including planarisation, etching,

deposition conductive or resistive layers on these semiconductor materials

treatment of these conductive layers, like planarisation, oxidation, etching, doping,

treatment of the insulating or conductive layers formed thereon,

planarisation of these semiconductor materials, or of the insulating and conductive layers formed thereon

References relevant to classification in this group
This subclass/group does not cover:
Formation of insulating layers on semiconductor wafers and the direct post-treatment of this formation
Formation of SOI
Special rules of classification within this group

The presence of a potential jump barrier need not to be specified. Inventions intended to be used in the fabrication of devices having a potential barrier may be classified under H01L 21/04.

[N: the devices having semiconductor bodies comprising semiconducting carbon, e.g. diamond, diamond-like carbon]
Definition statement
This subclass/group covers:

Passivation of semiconducting carbon, e.g. diamond

References relevant to classification in this group
This subclass/group does not cover:
Fullerenes, e.g. C60, C70
Carbon nanotubes
[N: the devices having semiconductor bodies comprising crystalline silicon carbide]
References relevant to classification in this group
This subclass/group does not cover:
Preparation of SiC wafers
Etching, polishing of semiconducting SiC
[N: using ion implantation]
Definition statement
This subclass/group covers:

Processes where ion implantation of boron and subsequent annealing does produce a p-doped region in a silicon carbide.

Special rules of classification within this group

Processes where ion implantation of boron and subsequent annealing does not produce a p-doped region are classified elsewhere, e.g. H01L 21/0445

[N: Oxidation and subsequent heat treatment of the foundation plate (H01L 21/165 takes precedence)]
References relevant to classification in this group
Reduction of the copper oxide or treatment of the oxide layer
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIII-BV compounds with or without impurities, e.g. doping materials [N: (H01L 21/041 to H01L 21/0425, H01L 21/045 to H01L 21/048 take precedence)]
Definition statement
This subclass/group covers:

Processes and apparatus which, by using the appropriate technology, are clearly suitable for manufacture or treatment of devices whose bodies comprise elements of the fourth group of the Periodic System or AIII-BV compounds, even if the material used is not explicitly specified.

References relevant to classification in this group
This subclass/group does not cover:
Processes for fabricating devices having semiconductor bodies of diamond
processes for fabricating devices having semiconductor bodies comprising crystalline silicon carbide
[N: Joining of semiconductor bodies for junction formation]
Definition statement
This subclass/group covers:

Joining through a metal layer or eutectic layer.

References relevant to classification in this group
This subclass/group does not cover:
Joining/bonding of semiconductor bodies through an oxide layer
[N: by direct bonding]
Definition statement
This subclass/group covers:

Direct bonding of semiconductor bodies without intermediate layer

Deposition of semiconductor materials on a substrate, e.g. epitaxial growth [N: solid phase epitaxy]
Special rules of classification within this group

Groups H01L 21/20 to H01L21/208C2 are no longer used for classification of documents, see H01L 21/02365 and subgroups.

Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; [N: Interactions between two or more impurities; Redistribution of impurities]
Definition statement
This subclass/group covers:

Plasma doping.

Special rules of classification within this group

Plasma doping is considered as doping from a gas phase, as is the case in Plasma Immersion Ion Implantation. Nevertheless, plasma doping can have ion implantation aspects like the type of ions. These aspects should be classified in ion implantation, H01L 21/265. But a group symbol e.g. H01L 21/2236 or an index code e.g. H01L 21/2236 should always be allocated to track the fact it uses a plasma.

using diffusion into or out of a solid from or into a gaseous phase [N: (H01L 21/221 to H01L 21/222 take precedence; diffusion through an applied layer H01L 21/225)]
References relevant to classification in this group
This subclass/group does not cover:
Diffusion of killers
Lithium-drift
Informative references
Attention is drawn to the following places, which may be of interest for search:
Diffusion through an applied layer
using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer [N: (H01L 21/221 to H01L 21/222 take precedence)]
References relevant to classification in this group
This subclass/group does not cover:
Diffusion of killers
Lithium-drift
[N: from or through or into an applied layer, e.g. photoresist, nitrides]
Special rules of classification within this group

In the range H01L 21/2254 to H01L 21/2257 the main compositional part of the applied layer just before the diffusion step has to be considered for classification

using diffusion into or out of a solid from or into a liquid phase, e.g. alloy diffusion processes [N: (H01L 21/221 to H01L 21/222 take precedence)]
References relevant to classification in this group
This subclass/group does not cover:
Diffusion of killers
Lithium-drift
Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body [N: (H01L 21/182 takes precedence)]
References relevant to classification in this group
This subclass/group does not cover:
Intermixing, interdiffusion or disordering of AIII-BV heterostructures
Bombardment with radiation [N: (H01L 21/3105 takes precedence)]
References relevant to classification in this group
This subclass/group does not cover:
Bombardment with radiation as post-treatment of an insulating layer
with high-energy radiation (H01L 21/261 takes precedence)
References relevant to classification in this group
This subclass/group does not cover:
High energy radiation creating a nuclear transmutation
Special rules of classification within this group

There is no exact border defining high energy. It is meant to cover alpha, beta, gamma, Röntgen ... rays. The sub group H01L 21/2633 is incorrectly placed as a subgroup.

producing ion implantation (ion beam tubes for localised treatment H01J 37/30)
Informative references
Attention is drawn to the following places, which may be of interest for search:
Ion beam tubes for localised treatment
H10J37/30
using masks [N: (H01L 21/26586 takes precedence)]
References relevant to classification in this group
This subclass/group does not cover:

This group does not cover.

Crystal planes or main crystal surface and ion beam present an angle
Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L 21/20 to H01L 21/268; [N: etching for patterning the electrodes H01L 21/311 and H01L 21/3213]
Definition statement
This subclass/group covers:

Includes processes for forming

- conductor-semiconductor,

- conductor-insulator-semiconductor, or

- conductor-insulator-conductor-insulator-semiconductor structures.

Multistep processes for manufacturing electrodes on semiconductor bodies characterized by

- a sequence of single steps, possibly including steps like deposition of semiconductor material, alloying, diffusion or ion implantation,

- the structure or the shape of the electrode,

- the electrode is part of a semiconductor device including a semiconductor body.

References relevant to classification in this group
This subclass/group does not cover:
Mono-step- processes: single diffusion of dopants alloying of electrode materials implantation of dopants
Multistep processes for forming capacitor electrodes
Informative references
Attention is drawn to the following places, which may be of interest for search:
Etching for patterning electrodes
Special rules of classification within this group

Formation of electrodes only involving an etching of conductive materials, including silicide on polysilicon: H01L 21/3213 and subgroups

Information peculiar to single-step processes should also be classified in the corresponding group, e.g.

- H01L 21/311 or H01L 21/3213 for etching,

- H01L 21/3105 or H01L 21/321 for planarising

[N: Making conductor-insulator-semiconductor electrodes]
Definition statement
This subclass/group covers:

Processes for the fabrication of conductor-insulator-semiconductor structure, wherein the conductor is part of the interconnect (gate level interconnect).

References relevant to classification in this group
This subclass/group does not cover:
Monosteps for forming insulators or conductors for which the application to gate electrodes is mentioned without further details.
[N: the insulator being formed after the semiconductor body, the semiconductor being silicon]
Definition statement
This subclass/group covers:

Deposition of the insulators, including epitaxial insulators, and the conductors within the same process or chamber.

[N: characterised by the conductor (H01L 21/28176 takes precedence)]
References relevant to classification in this group
This subclass/group does not cover:
Annealing, after the formation of the definitive gate conductor
Special rules of classification within this group

When the final conductor comprises a superconductor, subject matter is not classified according to H10L21/28E2B2 to H01L 21/28097, but instead it is classified in H01L 21/28026.

[N: the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities (H01L 21/28105 takes precedence)]
References relevant to classification in this group
This subclass/group does not cover:
the final conductor next to the insulator having a lateral composition or doping variation, or being formed laterally by more than one deposition step
Special rules of classification within this group

A very thin, e.g. silicon, adhesion or seed layer is not considered as the one next to the insulator

[N: the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer (formed by metal ion implantation H01L 21/28044)]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Silicide formed by metal ion implantation
Special rules of classification within this group

To assess the coverage of groups H01L 21/28052 and H01L 21/28061, barrier layers, e.g. TaSiN, are not considered]

[N: the conductor comprising a metal or metallic silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction (H01L 21/28052 takes precedence)]
References relevant to classification in this group
This subclass/group does not cover:
Conductors comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
Special rules of classification within this group

To assess the coverage of groups H01L 21/28052 and H01L 21/28061, barrier layers, e.g. TaSiN, are not considered]

[N: characterised by the sectional shape, e.g. T, inverted-T]
Special rules of classification within this group

Documents are also classified in groups H01L 21/28035 to H01L 21/28105 when the composition is also relevant

[N: Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects]
References relevant to classification in this group
This subclass/group does not cover:
Fabrication of lithographic masks for electrodes
Informative references
Attention is drawn to the following places, which may be of interest for search:
Lift-off aspects involving multilayer masks
[N: Making the insulator]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Forming insulating materials on a substrate
Special rules of classification within this group

In case the formation of the insulator would be of general interest, a group symbol should be given in H01L 21/02107.

[N: with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor]
Glossary of termsIn this group, the following terms (or expressions) are used with the meaning indicated:
In this subclass/group, the following terms (or expressions) are used with the meaning indicated:
RTN
Rapid Thermal Nitridation
RPN
Rapid Plasma Nitridation
[N: in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer (H01L 21/28194 and H01L 21/28202 take precedence)] [N: Note: thin oxidation layers used as a barrier layer or as a buffer layer, e.g. before the formation of a high-k insulator, are classified here only if important per se]
References relevant to classification in this group
This subclass/group does not cover:
Evaporation, ALD, CVD, sputtering, laser deposition
Nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
Special rules of classification within this group

Thin oxidation layers used as a barrier layer or as a buffer layer, e.g. before the fomation of a high-k insulator, are classified here only if important per se.

[N: by deposition of a layer, e.g. metal, metal compound or polysilicon, followed by transformation thereof into an insulating layer]
Special rules of classification within this group

In case the transformation would be of general interest it should be classified in

Deposition of conductive materials for electrodes [N: conducting electric current]
Definition statement
This subclass/group covers:

H01L 21/283 to H01L 21/2885 cover the deposition of conductive layers directly in contact with the semiconductor for forming electrodes.

References relevant to classification in this group
This subclass/group does not cover:
Formation of electrodes of capacitors, resistors, inductors
Special rules of classification within this group

Application to contacts must be mentioned with details. Moreover, details of deposition processes of conductive layers covered by H01L 21/3205 are additionally classified in this group and subgroups thereof. If a document discloses information relevant for any of the groups H01L 21/768 to H01L 21/76898, one or more of these groups should also be assigned.

from a gas or vapour, e.g. condensation
Definition statement
This subclass/group covers:

Methods for depositing conductive layers using gases or vapours of metals or metal-containing precursors.

References relevant to classification in this group
This subclass/group does not cover:
Deposition of polysilicon in contact with a semiconductor
Formation of electrodes of capacitors, resistors, inductors
Informative references
Attention is drawn to the following places, which may be of interest for search:
Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes
Special rules of classification within this group

The deposition process (PVD, CVD, ALD etc.) must be specially adapted for forming contacts or interconnects within semiconductor devices and must be disclosed in detail, i.e. include details on deposition parameters, precursor materials, particular apparatus details etc.

If a document discloses information relevant for any of the groups H01L 21/768 to H01L 21/76898, one or more of these groups should also be assigned.

[N: the conductive layers comprising semiconducting material (H01L 21/28518, H01L 21/28537 take precedence)]
References relevant to classification in this group
This subclass/group does not cover:
Conductive layers comprising silicides
Deposition of Schottky electrodes
Special rules of classification within this group

Deposition of polysilicon on silicon classified there only if application to contacts is mentioned. Otherwise H01L 21/02365

[N: Making of side-wall contacts]
Special rules of classification within this group

Deposition of polysilicon on silicon classified there only if application to contacts is mentioned. Otherwise H01L 21/02365

from a liquid, e.g. electrolytic deposition
Definition statement
This subclass/group covers:

The deposition of conductive layers directly in contact with semiconductors for forming electrodes using liquid deposition techniques, e.g. electroless plating.

References relevant to classification in this group
This subclass/group does not cover:
Formation of electrodes of capacitors, resistors, inductors
Informative references
Attention is drawn to the following places, which may be of interest for search:
Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating
Special rules of classification within this group

The deposition process must be specially adapted for forming contacts or interconnects within semiconductor devices and must be disclosed in detail, i.e. include details on deposition parameters, precursor materials, particular apparatus details etc.

If a document discloses information relevant for any of the groups H01L 21/768 to H01L 21/76898, one or more of these groups should also be assigned.

Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L 21/20 to H01L 21/26 (manufacture of electrodes thereon H01L 21/28)
Definition statement
This subclass/group covers:

- mechanical treatments, like grinding, sand blasting etc.

- hydrogenation of these semiconductors

- chemical treatments, like etching,

- formation of insulating layers and after treatment of these layers, like planarisation, etching, formation of conductive layers on these insulating layers and after treatment of these conductive layers and their doping.

References relevant to classification in this group
This subclass/group does not cover:
the treatment of metallic
the treatment of insulating layers
the treatment of II-VI compounds
Informative references
Attention is drawn to the following places, which may be of interest for search:
Manufacture of electrodes thereon
Mechanical treatment, e.g. grinding, polishing, cutting [N: (H01L 21/30625 takes precedence)]
Definition statement
This subclass/group covers:

Mechanical treatment of semiconductor wafers or semiconductor layers, except the mechanical treatment of insulating or conductive layers on semiconductor wafers.

Relationship between large subject matter areas

Mechanical treatment in general:

- grinding, polishing B24B,

- abrasive blasting B24C

References relevant to classification in this group
This subclass/group does not cover:
Polishing of semiconductor wafers
Polishing of epitaxial layers on semiconductor wafers
Mechanical treatment of insulating
Conductive layers on wafers
Single step mechanical operations, like sawing, polishing, breaking etc. classified in the corresponding group in section B
Special rules of classification within this group

The mere use of a machine is classified with the machine only.

Process for the mechanical treatment, enhanced by chemical treatment, is classified in chemical treatment, but may be given a group symbol in mechanical treatment if the mechanical treatment itself is of importance for the invention.

Purely mechanical polishing is considered as chemical-mechanical polishing, and is classified accordingly.

[N: Making grooves, e.g. cutting]
Definition statement
This subclass/group covers:

Making grooves, which may result in cutting

References relevant to classification in this group
This subclass/group does not cover:
Singulation of wafers into dies
Chemical or electrical treatment, e.g. electrolytic etching (to form insulating layers H01L 21/31)
Definition statement
This subclass/group covers:

Chemical or electrical treatment of group IV or III-V semiconductors.

Formation of porous semiconductors,

Functionalisation of semiconductor surfaces

References relevant to classification in this group
This subclass/group does not cover:
Chemical or electrical treatment to form insulating layers
[N: Anisotropic liquid etching (H01L 21/3063 takes precedence)]
Definition statement
This subclass/group covers:

Anisotropic liquid etching, i.e. "crystal orientation dependant" etching, using basic (pH>7) compositions. The etch composition is often composed of KOH, amines, azines, quaternary ammonium compounds

References relevant to classification in this group
This subclass/group does not cover:
Electrolytic etching
Anisotropic etching for tartarising surfaces
Informative references
Attention is drawn to the following places, which may be of interest for search:
Etching for fabrication of MEMs.
B81C1/00F2D2
[N: Vapour phase etching]
Definition statement
This subclass/group covers:

Reactive Ion Etching [RIE] of III-V

[N: With simultaneous mechanical treatment, e.g. mechanico-chemical polishing]
Definition statement
This subclass/group covers:

Processes for polishing semiconductors not being part of the sequence for preparing wafers from an ingot (H01L 21/02013 or H01L 21/02024).

Covers polishing or CMP of semiconductor layers deposited on a substrate, like epitaxial layers.

References relevant to classification in this group
This subclass/group does not cover:
Polishing or CMP of conductive layers
Polishing or CMP of insulating layers
Polishing or CMP of bulk wafers, wherein the polishing is part of the sequence for preparing wafers from an ingot
H01L21/00D2M2AH01L 21/02024
Special rules of classification within this group

Chemical-mechanical polishing also includes purely mechanical polishing.

Electrolytic etching
References relevant to classification in this group
This subclass/group does not cover:
formation of porous materials by electrolysis
Informative references
Attention is drawn to the following places, which may be of interest for search:
Electrolytic etching in general
Plasma etching; Reactive-ion etching
Definition statement
This subclass/group covers:

- sputter etching,

- particle (electron, ion, photon) beam enhanced etching

- light assisted etching.

- dry etching, without plasma

References relevant to classification in this group
This subclass/group does not cover:
Reactive ion etching of III-V materials
Informative references
Attention is drawn to the following places, which may be of interest for search:
Laser etching without reactive atmosphere per se
using masks (H01L 21/3063, H01L 21/3065 take precedence)
Definition statement
This subclass/group covers:

Masks used for patterning semiconductors of group IV or III-V, including masks used for plasma etching/patterning, excepted masks for electrolytic etching.

The fabrication of masks to be used for etching or patterning semiconductors (non-monocrystalline semiconductors being excluded).

References relevant to classification in this group
This subclass/group does not cover:
Electrolytic etching
Formation of masks for non patterning purposes, which are classified with the step in question: - masks for implantation - masks for forming insulating layers, - masks for selective growth, - masks for patterning semiconductors belonging to groups other than group IV and group III-V.
H01L 21/266, H01L 21/32, H01L21/02K4S3E3
Free standing masks, e.g. stencil masks
Formation of photoresist masks per se, except if the formation of the photoresist mask is specific to the device to be fabricated or semiconductor substrate
Formation and use of stencil masks
Informative references
Attention is drawn to the following places, which may be of interest for search:
Masks for patterning conductors, including polycrystalline or amorphous silicon
Masks for patterning insulating layers
General masks for patterning in the fabrication of semiconductor device
Special rules of classification within this group

A mask in H01L 21/00 is formed of a layer coated directly onto the surface of the wafer.

A free standing mask (stencil mask) laid on the wafer is not considered as a mask in the sense of H01L 21/00.

Masks are classified in H01L 21/308 only under the condition that its treatment or structure has been specially adapted to the fabrication of a device covered by H01L 21/00. Examples are:

- masks used for more than one technological step during device fabrication,

- masks whose structure, formation or treatment are adapted to the nature of the layers or materials used in the fabrication of semiconductor device, or to the device itself

The takes precedence rule (stemming from IPC) pointing to H01L 21/3065 is not valid for CPC: masks for etching by plasma or reactive ion etching are given a group symbol here.

Masks for electrolytic etching are classified with the electrochemical etching in H01L 21/3063.

Stencil masks for ion implantation are classified in H01L 21/266.

[N: characterised by their behaviour during the process, e.g. soluble masks, redeposited masks]
Definition statement
This subclass/group covers:

Masks having a specific behaviour during etching process. e.g. erodible mask, shrinking mask etc.

References relevant to classification in this group
This subclass/group does not cover:
Processes wherein the etching is interrupted to modify the mask (sequential etching), e.g. etching, followed by modifying the mask, followed by re-etching, with possible cycling of the above steps
[N: characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment]
Definition statement
This subclass/group covers:

Covers pre-treatment for the formation of a mask, post treatment of the mask before etching, treatments to modify the mask before use, e.g. hardening, formation of sidewalls, multiple sidewalls etc.

References relevant to classification in this group
This subclass/group does not cover:
Modification of the mask during etching
Removal of the mask after use
Informative references
Attention is drawn to the following places, which may be of interest for search:
Photoresist for lift
Inorganic masks for lift-off
[N: Process specially adapted to improve the resolution of the mask]
Definition statement
This subclass/group covers:

Process specially adapted to go below resolution limit of lithography.

to form insulating layers thereon, e.g. for masking or by using photolithographic techniques (layers forming electrodes H01L 21/28; encapsulating layers H01L 21/56); After treatment of these layers
Definition statement
This subclass/group covers:

Processes for forming insulating layers and their direct post-treatment.

To be used in any process, formation of interconnects, isolation oxides etc.when the invention is focussed on the insulator.

Informative references
Attention is drawn to the following places, which may be of interest for search:
Insulating layers forming part of electrodes
Encapsulating layers
After-treatment
Definition statement
This subclass/group covers:

Covers special treatments of insulating layers, wherein the special treatment is not a post-treatment as defined under H01L 21/00, i.e. the classical annealing of the insulating layer to improve its characteristics, but is for example

planarisation, patterning, functionalization after etching.

References relevant to classification in this group
This subclass/group does not cover:
Classical annealing after formation of the insulator, classified together with the formation
Special rules of classification within this group

Functionalization just after formation should be classified with the formation.

In case the process would also be of interest as a post treatment, both classes should be given.

[N: Planarisation of the insulating layers (H01L 21/31058 takes precedence)]
Definition statement
This subclass/group covers:
  • Planarisation of insulating layers.
  • Atomic scale planarisation (smoothening) of the insulating layers.
  • Reflow of insulating layers.
References relevant to classification in this group
This subclass/group does not cover:
After treatment, e.g. planarisation, of organic layers
[N: involving a dielectric removal step]
Definition statement
This subclass/group covers:

Planarisation involving a removal step not being a chemical etch step: this is the group for polishing and chemical-mechanical polishing (CMP) of insulating materials.

Informative references
Attention is drawn to the following places, which may be of interest for search:
Polishing slurries
[N: the removal being a chemical etching step, e.g. dry etching (etching per se H01L 21/311)]
Definition statement
This subclass/group covers:

Planarisation by non selective etching, e.g. by a blanket etching reducing the protrusions.

Informative references
Attention is drawn to the following places, which may be of interest for search:
Etching per se
[N: the removal being a selective chemical etching step, e.g. selective dry etching through a mask]
Definition statement
This subclass/group covers:

Processes where protrusions are selectively etched through a mask.

[N: Etching inorganic layers]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Etching glass
[N: by chemical means]
Definition statement
This subclass/group covers:

Etching by wet process, or by processes wherein gaseous reactants are condensed on the surface.

Special rules of classification within this group

Gaseous etch with HF is classified in H01L 21/31116

[N: by dry-etching]
Definition statement
This subclass/group covers:
  • Plasma etching
  • Ion beam etching
[N: Etching organic layers]
Definition statement
This subclass/group covers:

Removal of organic layers or polymers, including photoresists peculiar to semiconductor wafers or devices.

References relevant to classification in this group
This subclass/group does not cover:
The removal of silicon-containing compounds having an organic nature.
Informative references
Attention is drawn to the following places, which may be of interest for search:
Removal of photoresist not peculiar to semiconductor wafers
Special rules of classification within this group

Removal of photoresist being not peculiar to semiconductors is classified in G03F 7/42.

Peculiar to semiconductor devices means that particular precautions are taken to avoid influence of the removal of the photoresist on the semiconductor wafer or device.

[N: by chemical means]
Definition statement
This subclass/group covers:

Etching by wet process, or by processes wherein gaseous reactants are condensed on the surface.

[N: using masks]
Definition statement
This subclass/group covers:

Etching involving a specially adapted mask

Special rules of classification within this group

In case the mask would be of general interest, it should also be classified in H01L 21/033

Doping the insulating layers
Informative references
Attention is drawn to the following places, which may be of interest for search:
Doping with the purpose to alter resistivity or increase conductivity
See also after treatment of insulating layers
Special rules of classification within this group

Implantation or diffusion into insulating layers is also classified under H01L 21/02318 and subgroups.

Organic layers, e.g. photoresist (H01L 21/3105, H01L 21/32 take precedence; [N: photoresists per se G03C])
Informative references
Attention is drawn to the following places, which may be of interest for search:
Photoresists per se
Special rules of classification within this group

H01L 21/312 to H01L 21/3128 are no longer used for classification of new documents, see H01L 21/02112.

Inorganic layers (H01L 21/3105, H01L 21/32 take precedence)
Special rules of classification within this group

H01L 21/314 to H01L 21/3185 are no longer used for classification of new documents. See H01L 21/02112.

Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers (manufacture of electrodes H01L 21/28)
Definition statement
This subclass/group covers:

Deposition of conductive layers exclusively on insulating layers, when the process of deposition is relevant.

References relevant to classification in this group
This subclass/group does not cover:
Deposition of conductive layers on semiconductor
Special rules of classification within this group

When the technique of deposition is particular (CVD, PVD or electroplating), also classify in H10L21/283, H01L 21/285 or H01L 21/288. When an interconnection is concerned, see also H01L 21/768 and subgroups.

After treatment
Definition statement
This subclass/group covers:

Treatment of conductive layers, excluding formation of these layers. Includes:

- etching by chemical or physical means,

- planarisation, including chemical-mechanical polishing,

- oxidation, nitridation, or surface treatment,

- doping.

Polysilicon, amorphous silicon and silicides are considered as conductive materials for these groups.

Special rules of classification within this group

Polysilicon, amorphous silicon and silicides are considered as conductive materials for these groups. After treatment of layers of these materials is thus classified here.

For classifying in the group range H01L 21/321 to H01L 21/3215, the explicit presence of an insulating layer below the conductive or resistive layers is not mandatory.

[N: Oxidation of silicon-containing layers]
Definition statement
This subclass/group covers:

Oxidation of non-monocrystalline silicon, e.g. polycrystalline, microcrystalline or amorphous silicon.

References relevant to classification in this group
This subclass/group does not cover:
Oxidation of monocrystalline silicon
Special rules of classification within this group

Polysilicon, amorphous silicon and silicides are considered as conductive materials for these groups. Oxidation of layers of these materials is thus classified here.

For classifying in the group range H01L 21/321 to H01L 21/3215, the presence of an insulating layer below the conductive or resistive layers is not mandatory.

[N: Nitridation of silicon-containing layers]
Definition statement
This subclass/group covers:

Nitridation of non-monocrystalline silicon, e.g. polycrystalline, microcrystalline or amorphous silicon.

References relevant to classification in this group
This subclass/group does not cover:
Nitridation of monocrystalline silicon
Special rules of classification within this group

Polysilicon, amorphous silicon and silicides are considered as conductive materials for these groups. Nitridation of layers of these materials is thus classified here.

For classifying in the group range H01L 21/321 to H01L 21/3215, the explicit presence of an insulating layer below the conductive or resistive layers is not mandatory.

[N: Planarisation]
Definition statement
This subclass/group covers:

Planarisation of conductive or resistive layers.

Special rules of classification within this group

Polysilicon, amorphous silicon and silicides are considered as conductive materials for these groups. Planarisation of these layers is thus classified here.

For classifying in the group range H01L 21/321 to H01L 21/3215, the explicit presence of an insulating layer below the conductive or resistive layers is not mandatory.

[N: by chemical mechanical polishing (CMP)]
Informative references
Attention is drawn to the following places, which may be of interest for search:
CMP slurries
Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
Definition statement
This subclass/group covers:

Physical or chemical etching of conductive or resistive layers.

Etching of polysilicon layers

Etching of amorphous silicon layers

Informative references
Attention is drawn to the following places, which may be of interest for search:
Machines for plasma etching
Machines or apparatus for liquid etching
H10L21/67
Special rules of classification within this group

Polysilicon, amorphous silicon and silicides are considered as conductive materials for these groups. Etching of layers of these materials is thus classified here.

For classifying in the group range H01L 21/321 to H01L 21/3215, the explicit presence of an insulating layer below the conductive or resistive layers is not mandatory.

[N: by physical means only]
Definition statement
This subclass/group covers:

Etching processes, where no chemical reaction is involved, e.g.

sputtering, ion milling, laser ablation, pure ion beam etching.

Special rules of classification within this group

For classifying in the group range H01L 21/321 to H01L 21/3215, the explicit presence of an insulating layer below the conductive or resistive layers is not mandatory.

[N: of silicon-containing layers]
Definition statement
This subclass/group covers:

Silicides and silicon alloys.

[N: by chemical means only]
Definition statement
This subclass/group covers:

Use of Plasmas, e.g. RIE, and chemically assisted particle (ion or electron, photon) beam etching

Special rules of classification within this group

For classifying in the group range H01L 21/321 to H01L 21/3215, the explicit presence of an insulating layer below the conductive or resistive layers is not mandatory.

[N: by liquid etching only]
Definition statement
This subclass/group covers:

Etching with supercritical fluids

[N: using plasmas]
Definition statement
This subclass/group covers:

Etching assisted by electrons, ions and laser beams.

[N: of silicon-containing layers]
Definition statement
This subclass/group covers:

Polysilicon, amorphous, silicides, multilayers containing silicon

[N: pre- or post-treatments, e.g. anti-corrosion processes]
Definition statement
This subclass/group covers:

Pre-treatments before etching, including removal of natural oxide.

Anti-corrosion post-treatments.

References relevant to classification in this group
This subclass/group does not cover:
Post-treatment after etching, e.g. RIE
Special rules of classification within this group

In case the pre-treatment is a removal of natural oxide and is of general interest, a group symbol in H01L 21/02041 should be given.

In case the post treatment is a passivation by oxidation or nitridation this step should be classified independently.

For classifying in the group range H01L 21/321 to H01L 21/3215, the explicit presence of an insulating layer below the conductive or resistive layers is not mandatory.

[N: using masks]
Definition statement
This subclass/group covers:

Etching involving a mask specifically adapted to the etching operation.

References relevant to classification in this group
This subclass/group does not cover:
Classical photoresist masks, except if submitted to a special treatment, for example hardening, fluorination, etc.
Special rules of classification within this group

In case the mask would be of general interest, it should also be classified in H01L 21/033.

For classifying in the group range H01L 21/321 to H01L 21/3215, the explicit presence of an insulating layer below the conductive or resistive layers is not mandatory.

Doping the layers
Special rules of classification within this group

Polysilicon, amorphous silicon and silicides are considered as conductive materials for these groups. Doping of these layers is thus classified here.

For classifying in the group range H01L 21/321 to H01L 21/3215, the explicit presence of an insulating layer below the conductive or resistive layers is not mandatory.

to modify their internal properties, e.g. to produce internal imperfections
Definition statement
This subclass/group covers:
  • Treatments aimed at modifying the intrinsic properties of the crystals not otherwise provided for in H01L 21/00, like crystallographic defect rate.
  • Formation of defects for intrinsic or extrinsic gettering
References relevant to classification in this group
This subclass/group does not cover:
Modification of conductivity type
[N: of silicon bodies, e.g. for gettering]
Definition statement
This subclass/group covers:

Extrinsic gettering

Special rules of classification within this group

Gettering using both extrinsic and intrinsic gettering techniques is classified in both H01L 21/3221 and H01L 21/3225.

[N: Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering (H01L 21/3226 takes precedence)]
Definition statement
This subclass/group covers:

Intrinsic gettering

References relevant to classification in this group
This subclass/group does not cover:
Treatment of semiconductor bodies to modify their internal properties of silicon on insulator
Special rules of classification within this group

Gettering using both extrinsic and intrinsic gettering techniques is classified in both H01L 21/3221 and H01L 21/3225.

the devices having semiconductor bodies not provided for in groups [N: H01L 21/0405, H01L 21/0445], H01L 21/06, H01L 21/16 and H01L 21/18 with or without impurities, e.g. doping materials
Definition statement
This subclass/group covers:

Processes for fabricating devices having semiconductor bodies not belonging to group IV, IV-IV, III-V materials, or to Se, Te, CuO.

Processes for fabricating devices having semiconductor bodies based on II-VI materials.

References relevant to classification in this group
This subclass/group does not cover:
Inorganic semiconducting materials used for light detecting devices, e.g. I-III-VI materials, like CuInSe
Processes peculiar to the fabrication of light sensitive devices
Processes peculiar to the fabrication of inorganic light emitting devices
Special rules of classification within this group

As already evident from the limiting reference in the main group title of H01L 21/00, only fabrication processes relating to devices covered by main groups H01L 21/00 - H01L 29/00 should be classified under H01L 21/34.

- A single mention of an application in manufacturing devices covered by main groups H01L 21/00 - H01L 29/00, e.g. a junction FET, is sufficient to give a group symbol.

- at the other hand processes wherein the type of fabricated device is not mentioned at all will be considered to refer to devices not belonging to those covered by H01L 21/00 - H01L 29/00, and will consequently be classified together with the most probable application, e.g. H01L 31/00 for II-VI for light-sensitive devices.

[N: Multistep processes]
Special rules of classification within this group

The single step processes forming the multistep should also be classified independently of the multistep, provided the single step gives significant information.

Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
Definition statement
This subclass/group covers:

This group is not used for classification of new documents. Subject matter relating to the deposition of semiconductor materials is classified in H01L 21/02365.

Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions
Definition statement
This subclass/group covers:

Doping of II-VI materials.

Informative references
Attention is drawn to the following places, which may be of interest for search:
Semiconductor bodies composed of II-VI compounds for light sensitive devices
Bombardment with radiation
Definition statement
This subclass/group covers:

Radiation covers corpuscular as well as electromagnetic radiation

References relevant to classification in this group
This subclass/group does not cover:
Bombardment with radiation for etching purposes
Bombardment with radiation for deposition purposes
producing ion implantation (ion beam tubes for localized treatment H01J 37/30)
Informative references
Attention is drawn to the following places, which may be of interest for search:
Ion beam tubes for localized treatment
using masks
Definition statement
This subclass/group covers:

Processes for implantation wherein the invention is focused on the mask aspect, e.g. mask having a specific topography.

Informative references
Attention is drawn to the following places, which may be of interest for search:
Masks in general
Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L 21/36 to H01L 21/428
Definition statement
This subclass/group covers:

Electrodes on semiconductor materials as defined under H01L 21/34.

Covers the direct deposition of conductive materials on the semiconductor or through an insulating layer (Tunnel contact).

The group H01L 21/44 includes specific treatments of the semiconductor before formation of the contact (e.g. degenerescence by bombardment etc.).

References relevant to classification in this group
This subclass/group does not cover:
semiconductor materials of group IV or III-V
Deposition of conductive or insulating materials for electrodes
Definition statement
This subclass/group covers:

Insulating materials, only if the contact is a tunnelling contact.

from a liquid, e.g. electrolytic deposition
Definition statement
This subclass/group covers:
  • Electrolytic deposition
  • Electroless deposition
involving the application of pressure, e.g. thermo-compression bonding
Special rules of classification within this group

Classification is made in this group only if specific to the semiconductor material, or adapted to the type of device.

involving the application of mechanical vibrations, e.g. ultrasonic vibrations
Special rules of classification within this group

Classification is made in this group only if specific to the semiconductor material, or adapted to the type of device.

Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L 21/428 (manufacture of electrodes thereon H01L 21/44)
Definition statement
This subclass/group covers:

The treatment of semiconductor bodies including

- mechanical treatments, like grinding, sand blasting etc.

- chemical treatments, like etching,

- after-treatments of these semiconductors, like formation of insulating layers, planarisation or etching of these insulating layers, formation of conductive layers on these insulating layers and after treatment of these conductive layers and their doping.

Informative references
Attention is drawn to the following places, which may be of interest for search:
Manufacture of electrodes thereon
Chemical or electrical treatment, e.g. electrolytic etching (to form insulating layers H01L 21/469)
Informative references
Attention is drawn to the following places, which may be of interest for search:
Chemical or electrical treatment to form insulating layers thereon
using masks
References relevant to classification in this group
This subclass/group does not cover:
Masks used for patterning group IV and group III-V semiconductors
H10L21/308
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques (layers forming electrodes H01L 21/44; encapsulating layers H01L 21/56); After-treatment of these layers
Informative references
Attention is drawn to the following places, which may be of interest for search:
Layers forming electrodes
Encapsulating layers
organic layers, e.g. photoresist (H01L 21/475, H01L 21/4757 take precedence)
References relevant to classification in this group
This subclass/group does not cover:
Forming insulating layers using masks
After-treatment
Informative references
Attention is drawn to the following places, which may be of interest for search:
Formation of photoresist masks
Deposition of non-insulating, e.g. conductive -, resistive -, layers on insulating layers; After-treatment of these layers (manufacture of electrodes H01L 21/28, [N: H01L 21/44])
Informative references
Attention is drawn to the following places, which may be of interest for search:
Manufacture of electrodes
Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L 21/06 to H01L 21/326 ([N: apparatus therefor H01L 21/67; insulative sealing of leads in bases H01L 21/50]; containers, encapsulations, fillings, mountings per se H01L 23/00; [N: marking of parts H01L 23/544])
References relevant to classification in this group
This subclass/group does not cover:
Arrangements for connecting or disconnecting semiconductor or other solid state bodies, or methods related thereto, other than those
Informative references
Attention is drawn to the following places, which may be of interest for search:
Apparatus therefor
Insulating sealing of leads in bases
Containers, encapsulations, fillings, mountings per se
Marking of parts
Special rules of classification within this group

In this group, the expression "treatment" also covers the removal of leads from parts

Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L 21/06 to H01L 21/326, [N: e.g. sealing of a cap to a base of a container]
References relevant to classification in this group
This subclass/group does not cover:
Arrangements for connecting or disconnecting semiconductor or other solid state bodies, or methods related thereto, other than those
[N: Insulative] mounting semiconductor devices on supports [N: (H01L 21/563, H01L 23/49513 take precedence)]
Special rules of classification within this group

This group is no longer used for the classification of new documents as from June 1, 2010. The backlog of this group is being continuously reclassified to H01L 24/80 and subgroups.

Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; [N: Apparatus not specifically provided for elsewhere (processes per se H01L 21/30, H01L 21/46, H01L 23/00)]
Definition statement
This subclass/group covers:

the apparatus of the title and also the use of those apparatus

References relevant to classification in this sub group
This subclass/group does not cover:
Polishing apparatus
Welding apparatus
Apparatus for cutting semiconductor ingot
Coating apparatus
Electroplating apparatus
Optical measuring apparatus
Testing apparatus
Lithographic apparatus
Informative references
Attention is drawn to the following places, which may be of interest for search:
Cleaning in general
Robots in general
Electrostatic holders in general
Conveying in general
Cutting in general
Glossary of terms
In this subclass/group, the following terms (or expressions) are used with the meaning indicated:
Substrate
a substrate suitable for semiconductor or electric solid state devices or semiconductor or electric solid state components,e.g. a wafer
[N: Apparatus for fluid treatment (H01L 21/67126, H01L 21/6715 take precedence)]
Definition statement
This subclass/group covers:
  • Fluid delivery or exhaust systems (like plumbing, heat exchanger, valves systems, flow regulations means, pumping means) in direct connection with semiconductor manufacture or handling systems.
  • Atmosphere control systems in relation with semiconductor industry
References relevant to classification in this group
This subclass/group does not cover:
Details relating to the exhausts (e.g. pumps, filters, scrubber) of coating apparatus
Apparatus for sealing, encapsulating, glassing, decapsulating
Apparatus for applying a liquid, a resin, an ink
Informative references
Attention is drawn to the following places, which may be of interest for search:
Containers with atmosphere control
[N: for cleaning followed by drying, rinsing, stripping, blasting or the like]
Definition statement
This subclass/group covers:
  • Apparatus dealing with at least two processing steps taking place successively (like cleaning, drying, rinsing, stripping or blasting) are classified in this group.
  • Systems for only dry cleaning.
[N: Apparatus for mechanical treatment (for grinding or cutting, see the relevant groups in subclasses B24B or B28D)]
Definition statement
This subclass/group covers:
  • apparatus for dividing wafers into a plurality of parts (dicing),
  • apparatus for exerting a pressure on a substrate (like apparatus for bonding two wafers together),
  • apparatus for separating two bonded wafers.
References relevant to classification in this group
This subclass/group does not cover:
Cutting apparatus per se
Polishing apparatus
Apparatus for cutting semiconductor ingot
Informative references
Attention is drawn to the following places, which may be of interest for search:
Division of the substrate into plural individual devices
[N: mainly by conduction]
Definition statement
This subclass/group covers:
  • Apparatus where the substrate is in direct contact with the heating element
  • Heating elements with specific thermal properties (like thermal conductivity), e.g. materials of the heating element.
[N: mainly by convection]
Definition statement
This subclass/group covers:
  • Apparatus where the substrate is not in direct contact with the heating element
  • Thermal apparatus with cooling means, e.g. for temperature regulation
[N: mainly by radiation]
Definition statement
This subclass/group covers:

Thermal apparatus comprising lamps, Infra-Red light irradiation means or Ultra-Violet light irradiation means

[N: Apparatus for sealing, encapsulating, glassing, decapsulating or the like (processes H01L 23/02, H01L 23/28)]
Definition statement
This subclass/group covers:
  • Sealing arrangements (like O-ring) for a process chamber, a holding or transporting device
  • Slit valves or gates for closing the opening of a chamber
Informative references
Attention is drawn to the following places, which may be of interest for search:
Containers; Seals for semiconductor devices
Encapsulations, e.g. encapsulating layers, coatings for protection
[N: Apparatus for placing on an insulating substrate, e.g. tape]
Definition statement
This subclass/group covers:
  • All apparatus dealing with tapes (tape removal apparatus, tape placing apparatus)
  • Apparatus for removing dies from an adhesive tape (on which a severed wafer is placed).
[N: Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates]
Definition statement
This subclass/group covers:

Pick and Place apparatus (picking a die from a wafer and placing it on a different location).

[N: Apparatus for applying a liquid, a resin, an ink or the like (H01L 21/67126 takes precedence)]
References relevant to classification in this group
This subclass/group does not cover:
Apparatus for sealing, encapsulating, glassing, decapsulating
[N: comprising at least one ion or electron beam chamber (coating by ion implantation C23C; ion or electron beam tubes H01J 37/00)]
References relevant to classification in this group
This subclass/group does not cover:
Coating by ion implantation
Informative references
Attention is drawn to the following places, which may be of interest for search:
Ion or electron beam tubes
[N: comprising at least one polishing chamber (polishing apparatuses B24B)]
References relevant to classification in this group
This subclass/group does not cover:
Polishing apparatuses per se
[N: comprising at least one lithography chamber (lithographic apparatuses G03F 7/00)]
References relevant to classification in this group
This subclass/group does not cover:
Lithographic apparatuses per se
[N: comprising at least one plating chamber (electroless plating apparatuses C23C, electroplating apparatuses C25D)]
References relevant to classification in this group
This subclass/group does not cover:
Electroless plating apparatuses
Electroplating apparatuses
[N: Apparatus for monitoring, sorting or marking (testing or measuring H01L 22/00, marks per se H01L 23/544; testing individual semiconductor devices G01R 31/26)]
References relevant to classification in this group
This subclass/group does not cover:
Electrical testing individual semiconductor devices
Informative references
Attention is drawn to the following places, which may be of interest for search:
Testing or measuring
Marks per se
[N: Production flow monitoring, e.g. for increasing throughput (program-control systems per se G05B 19/00, e.g. total factory control G05B 19/418)]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Program-control systems per se
Total factory control
using specially adapted carriers [N: or holders; Fixing the workpieces on such carriers or holders (holders for supporting a complete device in operation H01L 23/32)]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Holders for supporting a complete device in operation
[N: Trays for chips (magazine for components H05K 13/0084)]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Magazine for components
[N: specially adapted for supporting large square shaped substrates (containers and packaging elements for glass sheets B65D 85/48, transporting of glass products during their manufacture C03B 35/00)]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Containers and packaging elements for glass sheets
Transporting of glass products during their manufacture
[N: specially adapted for containing substrates other than wafers (H01L 21/67356, H01L 21/67359 take precedence)]
References relevant to classification in this group
This subclass/group does not cover:
Closed carriers specially adapted for containing chips, dies or ICs
Closed carriers specially adapted for containing masks, reticles or pellicles
[N: characterised by materials, roughness, coatings or the like (materials relating to an injection moulding process B29C 45/00; chemical composition of materials C08L 51/00)]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Materials relating to an injection moulding process
Chemical composition of macromolecular compounds
[N: Mechanical details, e.g. roller, belt (H01L 21/67709 takes precedence)]
References relevant to classification in this group
This subclass/group does not cover:
Conveying using magnetic elements
[N: the substrates to be conveyed not being semiconductor wafers or large planar substrates, e.g. chips, lead frames, H01L 21/6773 takes precedence]
References relevant to classification in this group
This subclass/group does not cover:
Conveying cassettes, containers or carriers
[N: Mechanical parts of transfer devices (robots in general in B25J)]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Robots in general
[N: the wafers being stored in a carrier, involving loading and unloading (H01L 21/6779 takes precedence)]
References relevant to classification in this group
This subclass/group does not cover:
The workpieces being stored in a carrier, involving loading and unloading
[N: Mechanical parts of transfer devices (robots in general in B25J)]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Robots in general
[N: using air tracks]
Definition statement
This subclass/group covers:

Apparatus for moving substrates on a liquid track

[N: with angular orientation of workpieces (H01L 21/67787 and H01L 21/67793 take precedence)]
References relevant to classification in this group
This subclass/group does not cover:
Conveying with angular orientation of the workpieces
Conveying with orientating and positioning by means of a vibratory bowl or track
for positioning, orientation or alignment (for conveying H01L 21/677)
Informative references
Attention is drawn to the following places, which may be of interest for search:
Conveying
[N: Mask-wafer alignment (in general G03F7/20T, G03F9/00T)]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Alignment in general
G03F7/20T, G03F9/00T
for supporting or gripping (for conveying H01L 21/677, for positioning, orientation or alignment H01L 21/68)
Informative references
Attention is drawn to the following places, which may be of interest for search:
Conveying
Positioning, orientation or alignment
[N: using temporarily an auxiliary support]
References relevant to classification in this group
This subclass/group does not cover:
Temporary protection of the devices or parts of the devices during manufacture
B81C1/00K
[N: Wafer tapes, e.g. grinding or dicing support tapes (adhesive tapes in general C09J 7/02)]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Adhesive tapes in general
using mechanical means, e.g. chucks, clamps or pinches [N: (using electrostatic chucks H01L 21/6831)]
References relevant to classification in this group
This subclass/group does not cover:
Using electrostatic chucks
Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof (manufacture of assemblies consisting or preformed electrical components H05K 3/00, H05K 13/00)
Definition statement
This subclass/group covers:
  • Process for the integration of a plurality of solid state devices in or on a common substrate.
  • Processes for making isolation regions between components (e.g. LOCOS, STI etc.)
  • Processes for fabricating SOI substrates.
  • Processes for making interconnections between the solid state devices, on the surface of the substrate, or buried in the substrate, including specific treatments of these interconnections.
  • Processes for cutting wafers to singulate the devices, dicing.
  • Processes to fabricate devices consisting of a plurality of solid state components or integrated circuits of the bipolar, Field-Effect type and memories.
  • Process for the assembly on a common substrate of two or more components.
Informative references
Attention is drawn to the following places, which may be of interest for search:
Manufacture of assemblies consisting of preformed electrical components
Manufacture of specific parts of devices defined in group H01L 21/70 ([N: H01L 21/0405, H01L 21/0445], H01L 21/28, H01L 21/44, H01L 21/48 take precedence)
Definition statement
This subclass/group covers:
  • Multistep processes for the fabrication of buried regions, also used as buried connections between zones,
  • Multistep processes for the fabrication of zones providing electrical isolation between adjacent components,
  • Multistep processes for the fabrication of SOI wafers, for which the fabrication of devices has not started yet,
  • Multistep processes for the fabrication of interconnections between devices,
  • Multistep, processes for the fabrication of integrated circuits, bipolar technology, field-effect technology, CMOS, memories, IC based on combinations of these technologies,
  • Multistep processes for dicing wafers into individual devices.
References relevant to classification in this group
This subclass/group does not cover:
Processing of parts of devices based on carbon or diamond
Processing of parts of devices based on crystalline Silicon Carbide
Multistep processes for the manufacture of electrodes
Manufacture or treatment of parts prior to assembly of the devices, like leads, heat-sinks, etc.
Informative references
Attention is drawn to the following places, which may be of interest for search:
Wire-like connections
Making of [N: localized] buried regions, e.g. buried collector layers, internal connections [N: substrate contacts]
Definition statement
This subclass/group covers:

Multistep processes for the fabrication of buried regions, like buried collector layers, buried connections between zones, substrate contacts, as part of a component, e.g. formation of buried silicides.

Informative references
Attention is drawn to the following places, which may be of interest for search:
Diffusing impurities
Implanting impurities
[N: Making of internal connections, substrate contacts]
Definition statement
This subclass/group covers:

Fabrication of buried metallic or near metallic regions, like buried silicides, buried eutectic conductors.

Making of isolation regions between components
Definition statement
This subclass/group covers:
  • Fabrication of zones aimed at providing electrical isolation between adjacent components, i.e. dielectric regions (LOCOS, trench, shallow trench), air gaps, p-n junction or field effect.
  • Fabrication of SOI wafers, for which the fabrication of devices has not started yet.
Special rules of classification within this group

For subject matter classified in the range H01L 21/76 to H01L 21/765, when the isolation combines several techniques, both techniques are given a group symbol.

When the combination of several techniques involves the fabrication of SOI, a group symbol within the range H01L 21/76264 to H01L 21/76291 is given.

Single steps, like etching a trench, when they present a general interest or are specifically disclosed, should be given a group symbol in the corresponding single step covered by H01L 21/02 and sub groups.

Glossary of terms
In this subclass/group, the following terms (or expressions) are used with the meaning indicated:
horizontal
in the plane of the wafer
vertical
in a direction perpendicular to the plane of the wafer
Dielectric regions, [N: e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers]
Definition statement
This subclass/group covers:

Covers the formation of dielectric regions by

  • Oxidation of the substrate, or
  • Deposition of a dielectric, for example in a trench.
  • Formation of dielectric regions buried in the substrate, SOI
[N: using trench refilling with dielectric materials (trench filling with polycrystalline silicon H01L 21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L 21/76264)]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Trench filling with polycrystalline silicon
Trench filling with vertical isolation, e.g. trench refilling in a SOI substrate
[N: using semiconductor on insulator (SOI) technology (H01L 21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L 21/84; silicon on sapphire (SOS) technology H01L 21/86)]
Definition statement
This subclass/group covers:

The groups H01L 21/7624 to H01L 21/76291 cover the fabrication of a buried isolation region

References relevant to classification in this group
This subclass/group does not cover:
Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
Informative references
Attention is drawn to the following places, which may be of interest for search:
Manufacture of integrated circuits on insulating substrates
Silicon on sapphire (SOS) technology
Applying interconnections to be used for carrying current between separate components within a device [N: comprising conductors and dielectrics]
Definition statement
This subclass/group covers:

Multi-steps processes for manufacturing interconnections on the surface of a device or through the wafer.

References relevant to classification in this group
This subclass/group does not cover:
Fabrication of contacts
Internal interconnections
Fabrication of fuses and anti-fuses
Informative references
Attention is drawn to the following places, which may be of interest for search:
Cleaning
Formation of insulating layers
Etching of insulating or conductive layers
Formation or use of masks
Planarising insulating or conductive layers
Special rules of classification within this group

Information peculiar to single-step processes should also be classified in the corresponding sub group of H01L 21/02 (see informative references below).

Processes for fabricating fuses and anti-fuses are classified with the fuses and anti-fuses in H01L 23/525.

[N: by forming tapered via holes]
Definition statement
This subclass/group covers:

Methods specially adapted for forming via or contact holes having a wider top or bottom region, e.g. “cup-shaped” vias

Informative references
Attention is drawn to the following places, which may be of interest for search:
Etching insulating layers per se
[N: the opening being a via or contact hole penetrating the underlying conductor]
Definition statement
This subclass/group covers:

Methods of forming via or contact holes including a step of etching the conductor at the bottom of the hole so as to form e.g. a gouging feature;

methods of forming contact holes having a portion reaching into conductive regions (e.g. source and drain) of the semiconductor substrate

[N: involving intermediate temporary filling with material]
Definition statement
This subclass/group covers:

Methods of dual damascene processing involving intermediate temporary filling of the opening first formed in the process with material, e.g. planarisation to facilitate lithography of the second opening

Examples:

  • After formation of the via, the via is filled with a resin film 12 to provide for planarisation:::

US2006094221.

  • The dual damascene structure of a lower metal level 200 is filled with a sacrificial material 140 (see the figure below), then another metal level 202 having dual damascene structures 232 is fabricated. Finally, the sacrificial layer 140 is removed and all metal levels are metalized simultaneously:

US2005110145

References relevant to classification in this group
This subclass/group does not cover:
Conventional trench-first dual damascene methods in which the photoresist for forming the via hole fills the trench
[N: involving one or more buried masks]
Definition statement
This subclass/group covers:

Methods of dual damascene processing involving one or more buried masks, i.e. one or more pre-patterned mask or etch stop layers are fabricated prior to deposition of the trench-level dielectric.

Examples:

  • The etch stop 114 is pre-patterned and buried under ILD 118 (see the figure below):

WO2005109473

[N: involving multiple stacked pre-patterned masks]
Definition statement
This subclass/group covers:

Methods of dual damascene processing involving multiple stacked pre-patterned masks on the trench-level dielectric, i.e. mask stacks pre-defining the trench and via patterns before the actual etching process

Examples:

Layers 135, 140, 150 are hardmask layers, layer 180 is a photoresist for patterning layer 150. The dual damascene structure is transferred into the ILD 130 with the help of the stack of pre-patterned hardmasks 135, 140, 150:

US2003207207

[N: involving a partial via etch]
Definition statement
This subclass/group covers:

All dual damascene processes in which in an early stage a via is formed partially through the dielectric stack. The via etch is completed later in the process, e.g. during the etching step for forming the trench.

Examples:

US2006166482

First, the via is partially etched into the dielectric stack. In a later step, the via etch is completed together with the trench etch.

Special rules of classification within this group

Dual damascene processing also involving a stack of pre-patterned hard mask layers, the group symbol H01L 21/76811 is also assigned.

If the partial via process also includes a step of intermediate filling the partial via with a planarising material, the document needs to be classified in H01L 21/76808, too.

[N: after-treatment, e.g. cleaning or removal of oxides on underlying conductors; H01L 21/76831 takes precedence]
Definition statement
This subclass/group covers:

Particular method steps designed for improving the result of a process of forming an interconnect opening in a dielectric, e.g. removal of oxides from the surface of a conductor at the bottom of a via hole, removal of etching residues, or treatments restoring the dielectric at the sidewalls.

Examples:

After formation of the opening 10, the photoresist mask and etch residues are removed using a reducing plasma. During this treatment an undesired coating layer 14 forms on the sidewalls of opening 10. Layer 14 is eventually removed by the directional beam of charged oxidizing particles having its main axis 20 parallel to the sidewalls of opening 10:

US6673721

Note that in this case the sidewall layer 14 is an undesired by-product of a plasma treatment process. The document should therefore not be classified in H01L 21/76831.

After forming an opening in a low-k dielectric, a degassing treatment and a plasma treatment are carried out in order to remove methyl groups from the dielectric and an oxide from the underlying conductor 22A:

US2005272247

References relevant to classification in this group
This subclass/group does not cover:
After-treatment steps leading to the formation of modified sidewall layers
Special rules of classification within this group

If the method of after-treatment comprises aspects which are classified in any one of the subgroups H01L 21/76822+ (see below), the corresponding group should also be given. If the after-treatment leads to the formation of a sidewall layer in the opening comprising modified dielectric material, the group H01L 21/76831 should also be assigned (note, however, that if the sidewall insulation is formed by a conventional deposition step, H01L 21/76831 is the only relevant group).

H01L 21/76814 is essentially a multistep group, i.e. the after treatment step is only one of several steps to be carried out in order to form an interconnection. If a document exclusively relates to cleaning of openings in dielectrics (in a single-step fashion), the main group symbol is H01L 21/02063.

[N: aspects relating to the layout of the pattern or to the size of vias or trenches (layout of interconnections per se in H01L 23/528)]
Definition statement
This subclass/group covers:

The geometrical "aspects" to be classified in this group are mainly methodological aspects, e.g. step sequences leading to a reduction of the pitch between via holes, step sequences for incorporating a plurality of vias of different depth, methods of forming vias having a particular cross-sectional shape.

Examples:

Layer 230 is introduced into the structure to enable the simultaneous formation of a deep and a not-so-deep via. Although the formation of the vias themselves contains no special features at all, there is an aspect related "to the size of the vias":

US2006281290

Method for decreasing the pitch between adjacent contact holes by using a sequence of steps involving among other things a sacrificial pattern (13 in the figure below) and a conformal hardmask layer (14') to create an array of vias having a pitch below what is possible by standard lithography:

EP1818977

References relevant to classification in this group
This subclass/group does not cover:
Geometrical aspects relating to "tapered" vias, i.e. vias having a wider part somewhere
[N: using printing or stamping techniques]
Definition statement
This subclass/group covers:

Imprinting or stamping techniques for forming openings in dielectrics.

Methods using a stamp either to pattern a mask, e.g. a resist mask, for forming the opening or to imprint the opening directly into a dielectric

Example:

US7148142

[N: Smoothing of the dielectric (planarisation of insulating materials per se H01L 21/31051)]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Planarisation of insulating materials per se
[N: modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.]
Definition statement
This subclass/group covers:

All aspects related to forming or after-treatment steps which lead to a modification of the material of a dielectric layer within an interconnection structure.

Manufacture of "graded" dielectric layers having a varying composition throughout its thickness, no matter if said grading is achieved by a modified deposition process or an after-treatment.

Examples:

Graded dielectric layer: density and permittivity characteristics vary uniformly from a top portion to a bottom portion of the layer. The variation is achieved through varying deposition parameters such as flow rate of constituent process gases or deposition chamber pressure, or through a post deposition treatment, such as plasma treatment or curing:

US2006003598

The surface of the PSG layer 704 is made hydrophilic by a "scrubbing treatment" 710:

US2006003582

Special rules of classification within this group

It is not important whether the various treatment steps are conducted on a "main" interlevel or intralevel dielectric or on a "thin functional dielectric layer" as defined in H01L 21/76829 and subgroups.

If the treatment involves a patterned layer including an opening, the group H01L 21/76814 should also be given.

[N: transforming an insulating layer into a conductive layer]
Definition statement
This subclass/group covers:

Processes designed for rendering a dielectric layer of an interconnect stack conductive

Examples:

A diamond etch-stop layer (66 in the figure below) is rendered conductive by implanting Ti followed by thermal treatment.

US5990493

Special rules of classification within this group

A document classified in this group is additionally classified in H01L 21/76822 and subgroups thereof, whenever appropriate, the method of conversion involves a plasma treatment, or an ion implantation.

[N: by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc. (plasma treatment in H01L 21/76826)]
Definition statement
This subclass/group covers:

After-treatment or post-treatment process of dielectric layers of the interconnect stack involving particle radiation, e.g. removal of moisture etc. by UV or e-beam radiation, processes for modifying the dielectric constant of the layer, introduction of dopants into the dielectric by particle irradiation.

Examples:

A layer of silane is deposited onto a polymer dielectric layer 16. This layer is then exposed to UV light to initiate polymerization of the silane molecules to form an adhesion promoter layer 18 (or an etch stop or hard mask layer), and to react the adhesion promoter layer with low dielectric constant polymer layer 16:

US2005221606

The upper surface of the porous MSQ film 105 is treated by electron beam irradiation or by UV irradiation to reinforce the upper portion in the film 105:

US2006211235

References relevant to classification in this group
This subclass/group does not cover:
Removal of porogens for manufacturing porous dielectrics
Plasma treatment
Special rules of classification within this group

If the treatment is performed to form or modify a "thin functional" dielectric layer, e.g. an etch stop, one of the groups H01L 21/76829 is additionally assigned.

Curing of a dielectric precursor material is generally not considered an "after-treatment" but characterizes the formation of the dielectric layer per se, covered by H01L 21/02348.

[N: by contacting the layer with gases, liquids or plasmas]
Definition statement
This subclass/group covers:

Processes involving contacting a dielectric of an interconnect stack with gases, liquids or plasmas in order to modify the internal structure and/or properties of the dielectric, e.g. nitridation, removal of organic groups from the layer, introduction of dopants into the dielectric using gases, liquids or plasmas.

Examples:

a low-k dielectric is treated in a supercritical fluid after deposition, after via etching, to improve mechanical strength or repair plasma damage:

US2006073697

Plasma treatment 130 is carried out in order to decrease the C- or F- concentration in an upper layer 120a of the ILD 120:

US2006286793

Plasma treatment is carried out in order to modify the sidewalls of a damascene opening 218:

US6013581

Informative references
Attention is drawn to the following places, which may be of interest for search:
Supercritical fluid treatment after a via hole formation
Plasma treatment is carried out to form a modified sidewall layer in an opening
Special rules of classification within this group

If the plasma treatment is carried out to form a modified sidewall layer in an opening, the group symbol H01L 21/76831 must also be assigned.

[N: thermal treatment]
Definition statement
This subclass/group covers:

Thermal treatment for modifying the internal structure and/or properties of the dielectric of an interconnect stack, e.g. removal of moisture.

Example:

After completion of the deposition, the low-k dielectric layer 206 is subjected to a heat treatment in a nitrogen-free atmosphere to promote the out-gassing of the volatile materials 220 and especially of nitrogen and nitrogen compounds:

US2004121265

Informative references
Attention is drawn to the following places, which may be of interest for search:
Plasma annealing
Special rules of classification within this group

If the heat treatment is carried out in reactive atmospheres, i.e. inevitably involves modification of the dielectric material by e.g. introducing a further chemical element into the layer, e.g. plasma annealing, the group symbol H01L 21/76826 is additionally assigned.

[N: characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers]
Definition statement
This subclass/group covers:

All aspects related to the formation and the geometry of so-called "thin functional dielectric layers", e.g. etch-stop films or dielectric barrier or liner layers.

Examples:

Fabrication of an oxygen-doped low-k SiC etch-stop layer 230:

US2003085408

Nitride liner 130 imparts tensile stress in the underlying semiconductor to improve carrier mobility:

US2005233514

Silicon oxide layer 224 is formed on top of a low-k dielectric. Layer 224 serves as a sacrificial cap layer:

US2004121265

Special rules of classification within this group

If a document dealing with a thin functional dielectric layer also contains after-treatment aspects as defined in H01L 21/76822+, one (or more) of the latter groups should also be assigned to this document.

Glossary of terms
In this subclass/group, the following terms (or expressions) are used with the meaning indicated:

"Thin" layer as used herein means thin compared with the "main" interlevel or intralevel dielectric. In cases of doubt as to whether the layer is "thin" in the above sense, the criterion "functional layer" takes precedence, i.e. documents relating to layers, which may not exactly be "thin" in the above sense but serve some particular purpose except from merely isolating conductors, should also be classified here.

[N: in via holes and/or trenches, e.g. non-conductive sidewall liners]
Definition statement
This subclass/group covers:

Sidewall layers that are formed by direct deposition

Sidewall liners obtained by treatment of the sidewalls of the opening.

Examples:

Sidewalls of a porous dielectric are plasma-treated in order to form a carbon sealing layer 24 on via sidewalls 22:

US2006046472

Non-metallic layer 15, e.g. silicon carbide or boron carbide is deposited in a dual damascene opening and etched back to form sidewall spacers 19:

US6284657

Special rules of classification within this group

If the treatment has characteristics relating to any of the groups H01L 21/76822+, one (or more) of the latter groups should also be assigned.

[N: multiple layers]
Definition statement
This subclass/group covers:

Stacks of two or more thin “functional” dielectric layers, e.g. multiple etch stop layers, multiple trench liners.

Examples:

Composite adhesion/etch-stop multilayer (SiC layer 104 and SiOC layer 106) is formed; layer 104 is for improving adhesion between layers 100 and 106:

US2006110912

Multiple dielectric capping layers 616/622 and 620/624 are formed by gas cluster ion beam "infusion":

WO2006052958

Glossary of terms
In this subclass/group, the following terms (or expressions) are used with the meaning indicated:
"multiple"
two or more layers in direct contact with each other.
[N: formation of thin insulating films on the sidewalls and/or on top of conductors (H01L 21/76831 takes precedence)]
Definition statement
This subclass/group covers:

Insulating film covering some part of the conductor regardless of whether the conductor is "free-standing" or an inlaid conductor.

Example:

Dielectric film 107 covers the top and part of the sidewalls of inlaid conductors 105:

US2005087871

Temporary sacrificial encapsulation layer (206 in fig. 5, 306 in fig. 6) is formed in a dual damascene opening and covering an exposed underlying conductor in order to form a protective layer for subsequent cleaning steps:

US2006292863

References relevant to classification in this group
This subclass/group does not cover:
Dielectric sidewall liners in openings
[N: combinations of two or more different dielectric layers having a low dielectric constant (H01L 21/76832 takes precedence)]
Definition statement
This subclass/group covers:

Dielectric layer stacks in which e.g. the via-level dielectric and the trench-level dielectric comprise different low-k materials or in which e.g. the structure contains a low-k etch-stop or adhesion layer separating two dielectrics of which at least one must be a low-k dielectric.

Examples:

Trench-level dielectric (spin-on low-k dielectric 24) and via-level dielectric (CVD SiOC layer 10) are different low-k materials:

US2005130407

Via-level and trench-level dielectrics (204 and 212) are made of the same low-k material, but the etch-stop layer 206 is made of a different low-k material:

US2005263876

Posts (40) are made of a non-porous low-k dielectric whereas the material filling the spaces between the posts is a porous low-k dielectric:

US2005227480

References relevant to classification in this group
This subclass/group does not cover:
Middle etch-stop layer being a multilayer system
[N: filling up the space between adjacent conductive structures; gap-filling properties of dielectrics]
Definition statement
This subclass/group covers:

Special measures for improving the gap-filling properties of a dielectric, wherein said "gap" is formed between conductive structures. The term "gap" is also intended to include vertical gaps.

Example:

US2005186796:

a first dielectric (213) is deposited over conductive structures 207 and etched back (the figure above shows the layer 213 after etch-back) so as to partially fill the gap and reduce its aspect ratio, a second dielectric (217) fills the remaining gap.

[N: characterised by the formation and the after-treatment of the conductors (etching for patterning the conductors H01L 21/3213)]
Informative references
Attention is drawn to the following places, which may be of interest for search:
When the interconnect is also used as the conductor part of a conductor-insulator-semiconductor electrode (gate level interconnections)
Etching for patterning conductors
Special rules of classification within this group

Information peculiar to single-step processes should also be classified in the corresponding group, e.g.

- H01L 21/02041 for cleaning

- H01L 21/02697, H01L212/283 to H01L 21/288 and H01L 21/3105 for the formation of conductive layers,

- H01L 21/3213 for etching,

- H01L 21/321 for planarising, etc.

[N: formed in openings in a dielectric]
Definition statement
This subclass/group covers:

Thin conductive film being formed in an opening in a dielectric, e.g. barrier, adhesion, nucleation, seed or liner layers.

Example:

a barrier layer comprising e.g. Ru, Ir etc. or one of their (conducting) oxides is deposited in a trench or a dual damascene opening:

US2005206000

Informative references
Attention is drawn to the following places, which may be of interest for search:
Thin films serving as seed layer for electroplating
Special rules of classification within this group

All documents dealing with the formation of thin conductive films in openings should be classified in this group or one of its subgroups even if the fact that the thin film is formed in an opening is not an important aspect of the disclosure under consideration.

If the deposition method of the thin functional layer is disclosed in some detail (PVD, CVD, ALD, plating etc.), the corresponding groups H01L 21/28512 to H01L 21/2885 should also be assigned.

[N: bottomless liners]
Definition statement
This subclass/group covers:

At least one of the conductive thin films in the opening does not cover the bottom of the opening in its entirety, i.e. even when the thin film is removed from only a part of the bottom of the openings.

Examples:

a set of conductive barrier layers is deposited over the sidewalls of a porous dielectric and subsequently removed from the via floor by sputtering:

US6528409

Barrier layers covering only part of the sidewalls:

US2006246699

Multiple liner layers (30, 31, 33, 35) are deposited in a via of which only the outermost layers (30, 31) are removed from the via bottom:

US6555461

[N: layer combinations]
Definition statement
This subclass/group covers:

Layer combinations, i.e. arrangements of more than one layer, in the openings, e.g. combinations of particular materials other than the "standard" barrier combinations Ti/TiN, TaN/Ta or W/WN.

Superlattices comprising a multitude of layers comprising "standard" materials (Ti/TiN, TaN/Ta or W/WN), e.g. a TaN/Ta/TaN/Ta... superlattice.

Graded layers, e.g. a stack of infinitely thin multiple layers with varying composition.

Conductive thin film having a graded composition

Layer combinations formed on top of an inlaid conductor

In these cases the thin film is still considered as being formed "in an opening of a dielectric", see the further explanation and example (i) under point 1.4 below).

Examples:

43 is a TaN layer, 44 is a TaN layer having a graded content of N, 45 is an alpha-Ta layer:

US7033940

TaN/W/TaN/W/... nanolaminates, fabricated by ALD:

US2006079090

TaN/Ta/TaN/Ta stack:

US2005255691

Different barrier materials on the sidewalls and on the bottom of the via hole (α-phase Ta layer 24 is provided on the via bottom, while the sidewalls are covered with a β-phase Ta layer 29):

US 2004131878

[N: the layer being positioned within the main fill metal]
Definition statement
This subclass/group covers:

Conductive thin film formed within the "main" conductor filling the opening or where the opening is filled by a sequence of thin films. It is important, however, that said thin film does not comprise the same material as the main fill material.

Examples:

Barrier layer 54s, 54d separates two layers of fill metal:

US6028362

Trench filled by alternating layers 322, 324, comprising e.g. Co and Ni:

US2006264043

References relevant to classification in this group
This subclass/group does not cover:
Multistep plating forming a sequence of thin Cu films
[N: the layer being positioned on top of the main fill metal]
Definition statement
This subclass/group covers:

Conductive thin films, e.g. barrier, liner or adhesion layers, formed on top of an inlaid (i.e. damascene) conductor

Manufacture of electroless Co(Ni)WP capping layers on damascene conductors

CuSiN by siliciding and nitriding the surface of a Cu damascene conductor

Examples:

Cap layer 30 (CoWP layer) comprises multiple layers having periodic variations in the concentration of chemical elements:

WO2006020566

Electromigration barrier formed by depositing a metal layer 11, diffusing the metal into the underlying conductor and removing the remainder of layer 11:

WO03052798

[N: the layer covering a conductive structure; H01L 21/76849 takes precedence]
Definition statement
This subclass/group covers:

Thin functional conductive films covering interconnects not formed in an opening of a dielectric, e.g. on subtractive metal lines, e.g. a Ti/TiN adhesion/barrier stack on Al wiring.

Example:

Formation of a TiN layer (141) on an Al conductor (110). The method of fabrication avoids the formation of an unintentional Ti layer (140):

US2006099800

References relevant to classification in this group
This subclass/group does not cover:
Barrier or adhesion layers being positioned on top of the main fill metal, e.g. thin films formed on top of inlaid conductors
[N: the layer covering the sidewalls of the conductive structure]
Definition statement
This subclass/group covers:

Barrier, adhesion or other liner layers on the sidewalls or on top and on the sidewalls of a freestanding, e.g. subtractive, interconnect.

Examples:

US2005230262

US 2006180920

[N: characterized by particular after-treatment steps]
Definition statement
This subclass/group covers:

Conductive thin film treated in some way after it has been deposited. The resulting film must still be a conductive film.

Informative references
Attention is drawn to the following places, which may be of interest for search:
Methods of formation of barrier layers other than PVD, CVD or deposition from a liquids
Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
[N: after-treatment introducing at least one additional chemical element into the layer]
Definition statement
This subclass/group covers:

All methods introducing a new chemical element into the thin film, e.g. the reaction of the layer with the semiconductor substrate to form a silicide.

Example:

a titanium layer (black circles in the figure below) is deposited on the sidewalls of a dielectric layer, the Ti layer reacts with the oxygen (cross-hatched circles) contained in the dielectric during a later thermal step:

US2006214305

[N: by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner]
Definition statement
This subclass/group covers:

Contacting the thin film with a gas or a plasma so as to modify the composition of the layer, e.g. plasma nitriding.

Examples:

Refractive metal cap layer 303 is plasma nitrided to form a refractive metal nitride layer 305:

US6844258

Ru barrier layer 650b and a seed layer 666 are deposited in a trench, the seed layer is partially oxidized by exposing it to an oxidizing ambient. The oxide layer 667 serves as a protective layer and is dissolved when contacted with a plating bath:

US2006223310

[N: by diffusing alloying elements]
Definition statement
This subclass/group covers:

Introducing alloying elements, i.e. metallic elements, by diffusion into or reaction with pre-fabricated conductive thin film into.

Examples:

A barrier layer, an adhesion layer (Ti), a seed layer and a Cu fill are formed in a dual damascene opening; after planarisation, a thermal treatment is carried out to react the adhesion layer with the Cu thereby forming an interface layer having a graded Cu content:

US2006154465

Conductive thin film 608 (Ca film) is formed over an inlaid Cu line (601) and heat treatment is performed to diffuse Cu from the line into the Ca layer thereby forming a CuCa capping layer (606). The unreacted material of layer 608 is subsequently removed:

US6566262

References relevant to classification in this group
This subclass/group does not cover:
Layers itself being fabricated by the diffusion of alloying elements
Special rules of classification within this group

Diffusion is a bi-directional process, i.e. there can be cases where it cannot be unambiguously determined whether the final layer is the result of diffusing elements into the layer (which would constitute an example for the present class) or if the final film is the result of diffusing elements out of an original thin film, e.g. into the bulk conductor (this would pertain to H01L 21/76867, see the examples given there). In such cases both classes H01L 21/76858 and H01L 21/76867 should be assigned.

[N: by ion implantation]
Definition statement
This subclass/group covers:

Implantation methods, i.e. methods allowing for precise control of the energy of the implanted ions as well as of the implantation depth.

Examples:

Sn ions are implanted into barrier layer (440) in order to render the barrier amorphous and to introduce dopants having favourable electromigration properties:

US6835655

the surface of a CoWP capping layer (34) is nitrided by N2 ion implantation:

US2006175708

Informative references
Attention is drawn to the following places, which may be of interest for search:
Implantation in semiconductors
implantation in insulating layers
[N: after-treatment not introducing additional chemical elements into the layer]
Definition statement
This subclass/group covers:

Methods for removing contaminants, e.g. oxides, from thin functional conductive films.

Methods for transforming their grain structure.

Example:

Oxides and other contaminants of a Cu seed layer (144) are removed by a wet-chemical treatment:

US2005245072

[N: bombardment with particles, e.g. treatment in noble gas plasmas]
Definition statement
This subclass/group covers:

Contacting the film with plasmas or particles, e.g. high energy photons, while not introducing a new element into the film, e.g. treatment by UV irradiation for the removal of oxides.

Examples:

Barrier layer (Ti/TiN layer 118) is plasma treated to roughen the surface of the layer in the region 120. As a result, the number of nucleation sites is increased which slows down the growth of W layer 124:

US2005014358

Barrier layer (52) is subjected to a two-step redistribution process, i.e. overhanging portions (60) are removed and redistributed to reinforce sidewall regions (32, 34) where the PVD barrier is not thick enough. In a first step, this redistribution is achieved by bombardment with Ar and Ta ions with simultaneous deposition of Ta, in the second step, only Ar is used for material redistribution:

US2005260851

[N: thermal treatment]
Definition statement
This subclass/group covers:

Thermal treatment of thin functional films not introducing additional elements into the film, e.g. plasma annealing

Examples:

a Cu seed layer (228) is locally heat treated in order to induce grain growth in the seed layer:

US2006223311

a Ru barrier/seed layer (108) is annealed after deposition to remove oxides or other contaminants prior to plating:

US2005274622

References relevant to classification in this group
This subclass/group does not cover:
Film stacks, e.g. Ti/TiN and W, TaN/Ta and Cu, subjected to annealing after filling the contact hole
Informative references
Attention is drawn to the following places, which may be of interest for search:
Seed layers treated by an annealing step
Special rules of classification within this group

"Plasma annealing" should be classified here and in H01L 21/76862.

Note that for assigning this group symbol it is important that it is the thin film per se which is subjected to the thermal treatment. Thermal treatment of the main conductor is classified in H01L 21/76838 or, if the main conductor is formed in an opening in a dielectric, in H01L 21/76883.

Thermal treatments for driving an alloying element into the thin metal film are not classified here but in H01L 21/76858.

[N: selective removal of parts of the layer; H01L 21/76844 takes precedence]
Definition statement
This subclass/group covers:

Removal of overhanging or "necking" portions of conductive thin films at the upper regions of via holes, or all cases where sputter etching and sputter deposition are carried out simultaneously.

Examples:

Seed layer (10) is removed so as to provide a base layer for selective filling of the dual damascene trench;

US2006094220

Overhanging portions of a barrier layer 308 and/or a Cu seed layer (310) are removed and redistributed by gas cluster ion beam (GCIB) processing:

WO2004044954

Capping layer (106) on an underlying conductor (105) is partially etched off by sputtering; the sputtered material of barrier (106) is redistributed on the via sidewalls to form a bottomless first barrier:

US2006264030

References relevant to classification in this group
This subclass/group does not cover:
Forming a bottomless barrier
Informative references
Attention is drawn to the following places, which may be of interest for search:
Selective removal of a seed layer for electroplating
[N: characterized by methods of formation other than PVD, CVD or deposition from liquids (PVD in H01L 21/2855, CVD in H01L 21/28556 deposition from liquid in H01L 21/288))]
Definition statement
This subclass/group covers:

Formation of a functional conductive thin film, e.g. barrier, liner, adhesion or seed layers, by diffusing alloying elements such that they segregate at the surfaces of a conductor.

Diffusion of material from an initial thin film into a surface portion of the conductor, optionally followed by the removal of said initial thin film.

Examples:

A layer stack comprising a first barrier layer (6) and a metal layer (Hf, Zr, or Ti) suitable for forming an intermetallic compound with Cu is deposited in a dual damascene trench. A heat treatment forms layer (10b) comprising a compound of Cu and Hf, Zr, or Ti, while at the same time another compound layer (10a) is formed within the main conductor by diffusion of Hf, Zr, or Ti:

EP0881673

Barrier layer sections 6a, 6b are formed by diffusing material of the barrier layer 510 into the porous dielectric 2:

US2006154464

Al from Al layer 22 is diffused into inlaid Cu in order to form a CuAl electromigration barrier 12; the remaining unreacted Al layer is removed:

US2004207093

Informative references
Attention is drawn to the following places, which may be of interest for search:
PVD
CVD
Deposition from liquids
[N: forming or treating discontinuous thin films, e.g. repair, enhancement or reinforcement of discontinuous thin films]
Definition statement
This subclass/group covers:

Methods specially adapted for either forming a discontinuous thin functional conductive film or for treating a discontinuous film so as to make it continuous, e.g. repair of seed layers.

Example:

Ti layer 126 is formed only incompletely on the sidewalls of contact hole 124; the TiSix layer 132 repairs the discontinuities in layer 126:

US2005233577

[N: thin films associated with contacts of capacitors]
Definition statement
This subclass/group covers:

Thin conductive films formed in conjunction with the manufacture of contacts for capacitors

Example:

Formation of the barrier layer (13e):

US5699291

Informative references
Attention is drawn to the following places, which may be of interest for search:
Capacitor electrodes themselves
Special rules of classification within this group

This group is intended to sort of "filter out" all documents related to capacitor contacts providing a solution to the very specific problems encountered during the manufacture of capacitors. The groups H01L 21/76843, H01L 21/7685, H01L 21/76853, H01L 21/76867 should also be given, provided "interesting" aspects which might also be of importance in the context of more conventional barriers are disclosed.

[N: layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers]
Definition statement
This subclass/group covers:

Formation of seed, wetting, nucleation or catalyst layers.

Special rules of classification within this group

Whenever any one of the structural aspects covered by H01L 21/76843 or H01L 21/7685 applies the corresponding group symbol should be given in addition to the seed layer groups with the only exception that "layer combinations", i.e. structures containing stacks of seed layers, are not classified in H01L 21/76846.

Whenever any one of the after-treatment or manufacturing aspects covered by H01L 21/76853, H01L 21/76867 or H01L 21/76868 applies the corresponding group should also be given.

Documents related to seed layers are classified in the head group H01L 21/76871 only if it is not clear which deposition method is envisaged or if the corresponding seed layer is suitable for all three of the deposition methods listed below.

[N: for electroless plating]
Definition statement
This subclass/group covers:

Seed layers specifically adapted for facilitating the deposition of conductive films by electroless plating

Examples:

Formation of a Pd catalyst layer for electroless CoWP deposition on top of an inlaid Cu interconnect:

EP1496542

Formation of a Pd catalyst layer for electroless Cu plating (The Pd seed is formed by plasma-immersion ion implantation into a TaN barrier layer):

US2006040065

[N: by selective deposition of conductive material in the vias, e.g. selective CVD on semiconductor material, plating (plating on semiconductors in general H01L 21/288)]
Definition statement
This subclass/group covers:

Methods for selectively filling of vias or trenches in a dielectric layer with a conductive material, e.g. bottom up fill of a damascene opening not leading to a metal overburden on the field regions surrounding the opening.

Informative references
Attention is drawn to the following places, which may be of interest for search:
Plating on semiconductors in general
Special rules of classification within this group

If the deposition method is disclosed in some detail and includes one or more of PVD, CVD, ALD or liquid deposition, the corresponding group symbol H01L 21/2855, H01L 21/28556, H01L 21/28562, H01L 21/288 or H01L 21/2885 should also be assigned.

[N: by deposition over sacrificial masking layer, e.g. lift-off (lift-off per se H01L21/00B2)]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Lift-off of resists
Lift-off of other layers
[N: Post-treatment or after-treatment of the conductive material]
Definition statement
This subclass/group covers:

After-treatment for improving or modifying the result of the process of filling an opening in a dielectric layer, e.g. a via hole or a damascene trench, with conductive material.Thermal treatments before or after polishing, e.g. to induce grain growth, removal of metal residues, plasma cleaning

References relevant to classification in this group
This subclass/group does not cover:
Reflowing the conductor or applying pressure so as to better fill the opening
Plasma treatment specifically adapted for forming a thin layer on the surface of the conductor
Oxidation or otherwise rendering (parts of) the conductor non-conductive
Special rules of classification within this group

The after-treatment is part of a multi-step process for forming a conductor in an opening in a dielectric. Cleaning of conductors per se is classified in H01L 21/02068 to H01L 21/02074.

[N: by forming conductive members before deposition of protective insulating material, e.g. pillars, studs (H01L21/90C4 takes precedence)]
Definition statement
This subclass/group covers:

Conductors formed by through-mask plating

References relevant to classification in this group
This subclass/group does not cover:
Formation of pillars, studs, bumps etc. for connecting the semiconductor substrate to other substrates
Informative references
Attention is drawn to the following places, which may be of interest for search:
[N: Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances]
Definition statement
This subclass/group covers:

Methods in which the properties of an otherwise completed conductive member of an interconnect, i.e. the main conductor, are modified, e.g. by introducing dopants into the conductor, alloying the main conductor with another metal

References relevant to classification in this group
This subclass/group does not cover:
Processes for fabricating fuses and anti-fuses are classified with the fuses and anti-fuses in
Smoothing; Planarisation
Modification of thin functional conductive films such as barrier, adhesion, liner or seed layers
[N: Formation of self-aligned contacts, i.e. involving a lithographically uncritical step, e.g. to source/drain or emitter/base (self-aligned silicidation on field effect transistors H01L 29/66583)]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Self aligned silicidation on field effect transistors
[N: formed through a semiconductor substrate]
Definition statement
This subclass/group covers:

Establishing a conductive path extending through the substrate from the top surface to the bottom surface, e.g. through-silicon vias

Example

EP2426710A2

Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
Definition statement
This subclass/group covers:

In the group range H01L 21/77 to H01L 21/86 are classified processes for integration a plurality of solid state components formed in or on a common substrate, with

- H01L 21/77 and H01L21/77T covering the manufacturing of devices consisting of a plurality of solid state components formed or assembles on a common substrate, e.g. integrated circuits formed of a plurality of chips on a host substrate, and

- H01L 21/82 to H01L 21/86 covering the manufacturing of devices consisting of a plurality of solid state components formed in a common substrate, e.g. integrated circuits formed of a single chip, and

- H01L 21/78 to H01L 21/786 being reserved to processes for the division of a substrate into a plurality of individual devices.

References relevant to classification in this group
This subclass/group does not cover:
Integration processes for the manufacture of devices of the type classified in H01L 27/14 to H01L 27/32
Multistep methods for manufacturing random access memories [RAM] structures
Informative references
Attention is drawn to the following places, which may be of interest for search:
Devices sensitive to light
Devices adapted to emit light
Devices comprising thermo-electric components
Devices comprising superconductive components
Devices comprising piezo-electric, electro-strictive or magneto-strictive components
Devices comprising magneto-galvanic devices, e.g. Hall effect devices, MRAM
Devices comprising components for rectifying, amplifying or switching without a potential-jump barrier or surface barrier
Devices including bulk negative resistance effects, like Gunn devices
Devices comprising components using organic materials as active part
Components specially adapted for sensing light, electromagnetic or corpuscular radiation, or specially adapted for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
Devices with components specially adapted for light emission
Special rules of classification within this group

Integration processes for the manufacture of devices of the type classified in H01L 27/14 to H01L 27/32 are not classified in this group and its sub-groups. Instead, as they are peculiar to said devices, they are classified together with the devices.Multistep processes for manufacturing memory structures in general using field effect technology are covered by H01L27/105M; Multistep processes for manufacturing dynamic random access memory structures are covered by H01L 27/10844; Multistep processes for manufacturing static random access memory structures are covered by H01L 27/11;Multistep processes for manufacturing read-only memory structures are covered by H01L 27/112;Multistep processes for manufacturing electrically programmable read-only memory structures are covered by H01L 27/115

[N: comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs]
Definition statement
This subclass/group covers:

Multistep processes for the fabrication of devices comprising a plurality of TFT on an insulating substrate, e.g. for driving LCD displays.

Informative references
Attention is drawn to the following places, which may be of interest for search:
Recrystallization of amorphous or polycrystalline semiconductor layers
LCD displays per se
Special rules of classification within this group

If a single step among the multistep sequence appears to be particular it should be given a group symbol in the corresponding single step group.

with subsequent division of the substrate into plural individual devices (cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L 21/304)
Definition statement
This subclass/group covers:

Multistep processes for singulating devices.

References relevant to classification in this group
This subclass/group does not cover:
Devices sensitive to light
Light emitting devices
Informative references
Attention is drawn to the following places, which may be of interest for search:
Single mechanical steps like cutting semiconductors
Laser dicing
Single mechanical steps of grinding, lapping and polishing in general
Fine working of crystals, e.g. semiconductors
[N: involving the separation of the active layers from a substrate]
Definition statement
This subclass/group covers:

Separation of layers comprising active devices from the substrate, e.g. splitting after Epitaxial Lift-Off

Glossary of terms
In this subclass/group, the following terms (or expressions) are used with the meaning indicated:
ELO
Epitaxial Lift-Off
to produce devices, each consisting of a single circuit element (H01L 21/82 takes precedence)
Special rules of classification within this group

This group is not used

the substrate being a semiconductor body
Special rules of classification within this group

This group is not used

the substrate being other than a semiconductor body, e.g. insulating body
Definition statement
This subclass/group covers:

Division of the substrate into individual components where the process is peculiar to the insulating body or substrate.

to produce devices, e.g. integrated circuits, each consisting of a plurality of components
Definition statement
This subclass/group covers:

Multistep processes of integration of devices consisting of a plurality of solid state components formed in a common substrate, i.e. integrated circuits formed of a single chip.

Informative references
Attention is drawn to the following places, which may be of interest for search:
Integrated circuits
Special rules of classification within this group

Within the group range H01L 21/82 to H01L 21/86, a particular aspect linked to the fabrication of several components must appear. When the multistep processes do not show specific aspects linked to the fabrication of several components, e.g. when the integrated circuit is only constituted of a multiplicity of an identical device without further specification, then the process may only be classified with the multistep process for fabrication of this device, e.g. in H01L 29/00. Thus, the mere mention of the fabrication of an integrated circuit, when the fabrication of a device is disclosed, does not require a group symbol in H01L 21/82.

When the fabrication process is specified or peculiar to an electric circuit, only a group symbol in H01L 27/00 is given.

Combination of field effect devices and passive devices is classified in H01L 27/00.

[N: Three dimensional integrated circuits stacked in different levels]
Definition statement
This subclass/group covers:

Three dimensional integrated circuits in a common substrate

References relevant to classification in this group
This subclass/group does not cover:
The fabrication of three-dimensional integrated devices by assembling different devices or substrates
[N: with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface (with a current flow parallel to the substrate surface H01L 21/823431)]
Informative references
Attention is drawn to the following places, which may be of interest for search:
With a current flow parallel to the substrate surface
[N: with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface (with a current flow parallel to the substrate surface H01L 21/823821)]
Informative references
Attention is drawn to the following places, which may be of interest for search:
With a current flow parallel to the substrate surface
Memory structures
Special rules of classification within this group

This group is no longer used for classification of new documents. Subject matter relating to memory structures is covered by H01L27/105M.

Groups H01L21/8244 - H01L21/8247S have been removed from the CPC scheme. Their subject matter is now covered by H01L 27/11 and subgroups.

Assembly of devices consisting of solid state components formed in or on a common substrate; Assembly of integrated circuit devices (H01L 21/50 takes precedence; assemblies per se H01L 25/00)
Definition statement
This subclass/group covers:

Processes to fabricate devices formed of an assembly of a multiplicity of components on a host substrate.

References relevant to classification in this group
This subclass/group does not cover:
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L 21/06 to H01L 21/326
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
Testing or measuring during manufacture or treatment [N: or reliability measurements, i.e. testing of parts followed by no processing which modifies the parts as such (detecting or counting or handling H01L 21/67; marks, test patterns H01L 23/544; after manufacture G01R 31/26)]
Definition statement
This subclass/group covers:

Testing, measuring and applying procedures during manufacture of devices as defined under H01L 21/00, with the aim to

- to detect defects, to repair defects or to sort defective devices or wafers, or

- control the semiconductor device fabrication process,

- with or without corrective action on the process,

which are specific to semiconductor device fabrication.

Includes process end point determination.

Covers the measuring of a single parameter or variable

Relationship between large subject matter areas

Processes which are not specific to semiconductor fabrication, or where the semiconductor device could be interchanged with another product without needing to change the invention are typically not classified in H01L 22/00, but are classified in G01N or G01R.

References relevant to classification in this group
This subclass/group does not cover:
Contactless testing of integrated circuits,
Testing and controlling photoresist and lithographic patterns
G03F7/20T22
Semiconductor factory control
Informative references
Attention is drawn to the following places, which may be of interest for search:
Detecting parts, counting parts, handling parts
Marks on wafers, test patterns on wafers
Means for detecting end-point in lapping or polishing machines
Analysing materials by determining their chemical or physical properties
Optical characterization of semiconductors
Measuring electrical or magnetic variables
Multiple probes for testing, e.g. probe cards
Testing of individual devices, including on wafers, after manufacture
Testing of integrated circuits, including on wafers, after manufacture
Multiple probes for testing, e.g. probe cards
Inspection of images, flaw detection
Testing storing means, like memories, including repair
Measuring and control of plasma parameters
Controlling gas-filled discharge tubes, e.g. plasma machines, by information coming from substrate; end-point detection
H01J37/32D1C1
[N: Measuring as part of the manufacturing process (H01L 22/20 takes precedence; burn-in G01R31/28C8)]
Definition statement
This subclass/group covers:

Methods for measurement of structural or electrical parameters as part of the device manufacturing process.

Measuring as part of the manufacturing process; the parameter may be for example the thickness of layers, refractive index of layers, line width, warp of wafers, bond strength, defect concentration, metallurgic parameters, diffusion depth, dopant concentration.

Relationship between large subject matter areas

Measurement of parameters wherein the fabrication of semiconductor devices is not particularly relevant to the invention, or wherein the measurement of the parameter could equally be applied to the fabrication of other products than semiconductor products are typically not classified.

References relevant to classification in this group
This subclass/group does not cover:
Procedures, i.e. sequence of activities consisting of a plurality of measurement and correction, marking or sorting steps
Informative references
Attention is drawn to the following places, which may be of interest for search:
Measurement of parameters which is not part of the device fabrication processMeasurement of parameters wherein the fabrication of semiconductor devices is not particularly relevant to the invention, and wherein the measurement of the parameter could equally be applied to the fabrication of other products than semiconductor devices
Burn-in
G01R31/28C8
Special rules of classification within this group

In H01L 22/00, the method for measuring a parameter is classified in H01L 22/20 as soon as it is part of a testing or controlling procedure.

[N: for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions (electrical measurement of diffusions H01L 22/14)]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Electrical measurement of diffusion regions
[N: Procedures, i.e. sequence of activities consisting of a plurality of measurement and correction, marking or sorting steps]
Definition statement
This subclass/group covers:

Multi-step processes comprising at least a measuring step followed by a correcting, marking or sorting step.

References relevant to classification in this group
This subclass/group does not cover:
Semiconductor factory control
Informative references
Attention is drawn to the following places, which may be of interest for search:
Procedures applied to semiconductor fabrication but wherein the fabrication of semiconductor devices is not particularly relevant to the invention and wherein the procedure could equally be applied to the fabrication of products other than semiconductor devices are typically classified in
[N: Optical enhancement of defects or not directly visible states, e.g. selective electrolytic deposition, bubbles in liquids, light emission, colour change (voltage contrast G01R 31/311)]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Voltage contrast
[N: Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement]
Informative references
Attention is drawn to the following places, which may be of interest for search:
methods for plasma etching end point control
Special rules of classification within this group

End point process detection, when it is exclusively based on the use of a machine which has been designed for that purpose, need not to be classified in H01L 22/00.

Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line (switching, multiplexing, gating devices G01R 19/25; process control with lithography, e.g. dose control, G03F 7/20; structures for alignment control by optical means G03F7/20T8)
Informative references
Attention is drawn to the following places, which may be of interest for search:
Switching, multiplexing, gating devices
Process control with lithography, e.g. dose control
Structures for alignment control by optical means
G03F7/20T8
Process control influencing process steps in general, e.g. CD correction by etch or diffusion
Details of semiconductor or other solid state devices
Definition statement
This subclass/group covers:
  • Details of semiconductor or other solid state devices including
  • Structural arrangements for protection of semiconductor or other solid state devices against mechanical damage or moisture
  • Containers or seals
  • Mountings
  • Fillings or auxiliary members in containers of encapsulations
  • Encapsulations
  • Holders for supporting the complete device in operation
  • Arrangements for cooling, heating, ventilating or temperature compensation
  • Arrangements for conducting electric current to or from the solid state body in operation
  • Arrangements for conducting electric current within the solid state body in operation
  • Marks applied to semiconductor or other solid state devices
  • Protection against radiation of semiconductor or other solid state devices
  • Structural electrical arrangements for semiconductor or other solid state devices not otherwise provided for
References relevant to classification in this group
This subclass/group does not cover:
Micro-structural devices or systems, e.g. micro-mechanical devices
Arrangements for connecting or disconnecting semiconductor or solid-state bodies, and methods related thereto
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
Details of semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier
Details peculiar to semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
Details peculiar to semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission
Details peculiar to thermo-electric devices comprising a junction of dissimilar materials
Details peculiar to thermoelectric devices without a junction of dissimilar materials
Details peculiar to devices using superconductivity
Details peculiar to piezo-electric devices; electrostrictive devices; magnetostrictive devices
Details peculiar to devices using galvano-magnetic or similar magnetic effects
Details peculiar to solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier
Details peculiar to bulk negative resistance effect devices
Details peculiar to solid state devices not provided for in groups H01L 27/00 to H01L 47/00 and H01L 51/00 and not provided for in any other subclass
Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part
Informative references
Attention is drawn to the following places, which may be of interest for search:
Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
Laser working of semiconductors
B23K26/00F3
Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
Injection moulding of electrical components
Optical interconnections, e.g. light guides
Photolithography
Record carriers for use with machines and containing semiconductor elements (credit cards, id cards)
Structure or manufacture of flux-sensitive heads using magneto-resistive devices or effects
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
C11C11/00
Shape of semiconductor body
Device electrodes
Apparatus or processes specially adapted for manufacturing, assembling, maintaining, or repairing of line connectors or current connectors or for joining electric conductors (soldering / welding)
Special rules of classification within this main group

The use of Indexing Codes of the indexing scheme H01L 23/00 - H01L 23/66 is mandatory for additional information.

Glossary of terms
In this subclass/group, the following terms (or expressions) are used with the meaning indicated:
Parts
All structural units which are included in a complete device
Container
Enclosure forming part of the complete device and is essentially a solid construction in which the body of the device is placed, or which is formed around the body without forming an intimate layer thereon. Generally comprises a base, a lid and leads for electrical connection
Encapsulation
Enclosure which consists of one or more layers formed on the body and in intimate contact therewith
Containers; Seals
References relevant to classification in this group
This subclass/group does not cover:
Mountings
Arrangements for cooling, heating, ventilating or temperature compensation
Arrangements for conducting electric current to or from the solid state body in operation
Protection against radiation
High-frequency adaptations
Containers for imagers, i.e. semiconductor components sensitive to radiation
Informative references
Attention is drawn to the following places, which may be of interest for search:
Housings for MEMs
Housings for sensors in general
Housings for acceleration sensors
Housings for computers
Housings for record carriers, e.g. memory cards
Housings for memories
the leads having a passage through the base
References relevant to classification in this group
This subclass/group does not cover:
The leads being parallel to the base
Mountings, e.g. non-detachable insulating substrates
Informative references
Attention is drawn to the following places, which may be of interest for search:
Chip carriers per se
Multi-chip modules in general
Printed circuit boards
Semiconductor insulating substrates
Informative references
Attention is drawn to the following places, which may be of interest for search:
Semiconductor conductive substrates
Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
Definition statement
This subclass/group covers:

Additional parts and fillings within container or encapsulation, e.g. stiffeners, spacing layers.

References relevant to classification in this group
This subclass/group does not cover:
Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
Protection against radiation
gaseous at the normal operating temperature of the device
References relevant to classification in this group
This subclass/group does not cover:
Materials for absorbing or reacting with moisture or other undesired substances
liquid at the normal operating temperature of the device
References relevant to classification in this group
This subclass/group does not cover:
Materials for absorbing or reacting with moisture or other undesired substances
Solid or gel at the normal operating temperature of the device
References relevant to classification in this group
This subclass/group does not cover:
Materials for absorbing or reacting with moisture or other undesired substances
Double encapsulation or coating and encapsulation
Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
References relevant to classification in this group
This subclass/group does not cover:
Protection against radiation
Informative references
Attention is drawn to the following places, which may be of interest for search:
Insulating layers for contacts or interconnections
containing a filler
References relevant to classification in this group
This subclass/group does not cover:
Organo-silicon compounds
Partial encapsulation or coating
Informative references
Attention is drawn to the following places, which may be of interest for search:
Mask layer used as insulation layer
Coating or filling in grooves made in the semiconductor body
References relevant to classification in this group
This subclass/group does not cover:
Fillings of grooves in memory cells (e.g. capacitors of RAMs)
Holders for supporting the complete device in operation, i.e. detachable fixtures
References relevant to classification in this group
This subclass/group does not cover:
Mountings or securing means for detachable cooling or heating arrangements
Informative references
Attention is drawn to the following places, which may be of interest for search:
Connectors, e.g. sockets, in general
For printed circuits
Arrangements for cooling, heating, ventilating or temperature compensation; temperature sensing arrangements
Informative references
Attention is drawn to the following places, which may be of interest for search:
Temperature control of computers
Thermal treatment apparatus
Thermal control of PCBs
Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
References relevant to classification in this group
This subclass/group does not cover:
Encapsulations
Mountings or securing means for detachable cooling or heating arrangements
Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
The complete device being wholly immersed in a fluid other than air
Involving the transfer of heat by flowing fluids
Informative references
Attention is drawn to the following places, which may be of interest for search:
Arrangements for heating
Cooling facilitated by shape of device
References relevant to classification in this group
This subclass/group does not cover:
Cooling arrangements using the Peltier effect
Mountings or securing means for detachable cooling or heating arrangements
Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
Cooling arrangements with the complete device being wholly immersed in a fluid other than air
Cooling arrangements involving the transfer of heat by flowing fluids
Foil-like cooling fins or heat sinks
References relevant to classification in this group
This subclass/group does not cover:
Heat sinks being part of lead-frames
Ceramic materials or glass
References relevant to classification in this group
This subclass/group does not cover:
Cooling facilitated by selection of materials: diamonds
Cooling facilitated by selection of materials: having a heterogeneous or anisotropic structure
Cooling facilitated by selection of materials: laminates or multilayers
Cooling facilitated by selection of materials: organic materials with or without a thermoconductive filler
Cooling facilitated by selection of materials: semiconductor materials
Diamonds
Informative references
Attention is drawn to the following places, which may be of interest for search:
Diamond per se
having a heterogeneous or anisotropic structure, e.g. powder or fibres in a matrix, wire mesh, porous structures
References relevant to classification in this group
This subclass/group does not cover:
Cooling facilitated by selection of materials: diamonds
Cooling facilitated by selection of materials: organic materials with or without a thermoconductive filler
Metallic materials
References relevant to classification in this group
This subclass/group does not cover:
Cooling facilitated by selection of materials: diamonds
Cooling facilitated by selection of materials: having a heterogeneous or anisotropic structure
Cooling facilitated by selection of materials: laminates or multilayers
Cooling facilitated by selection of materials: organic materials with or without a thermoconductive filler
Cooling facilitated by selection of materials: semiconductor materials
for stacked arrangements of a plurality of semiconductor devices
Informative references
Attention is drawn to the following places, which may be of interest for search:
Assemblies consisting of a plurality of individual semiconductor or other solid-state bodies
Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
Informative references
Attention is drawn to the following places, which may be of interest for search:
Heating
Selection of materials for the device
Cooling by change of state, e.g. use of heat pipes
Informative references
Attention is drawn to the following places, which may be of interest for search:
Cooling by liquefied gas
Auxiliary members in encapsulations
References relevant to classification in this group
This subclass/group does not cover:
Leadframes specifically adapted to facilitate heat dissipation
the complete device being wholly immersed in a fluid other than air
References relevant to classification in this group
This subclass/group does not cover:
Cooling by change of state
involving the transfer of heat by flowing fluids
References relevant to classification in this group
This subclass/group does not cover:
Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
Cooling arrangements with the complete device being wholly immersed in a fluid other than air
by flowing gases, e.g. air
References relevant to classification in this group
This subclass/group does not cover:
Cooling involving the transfer of heat by flowing liquids
by flowing liquids
References relevant to classification in this group
This subclass/group does not cover:
Auxiliary members in containers: bellows
Auxiliary members in containers: pistons
Jet impingement
References relevant to classification in this group
This subclass/group does not cover:
Auxiliary members in containers: in combination with jet impingement
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements, selection of materials therefor
Informative references
Attention is drawn to the following places, which may be of interest for search:
Terminals, leads in general
Arrangements for connecting or disconnecting semiconductor or other solid-state bodies, and methods related thereto
consisting of lead-in layers inseparably applied to the semiconductor body
References relevant to classification in this group
This subclass/group does not cover:
Electrodes of semiconductor devices
consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
References relevant to classification in this group
This subclass/group does not cover:
Lead-in layers inseparably applied to the semiconductor body: bridge structures with air gap
Lead-in layers inseparably applied to the semiconductor body: beam leads
Lead-in layers inseparably applied to the semiconductor body: pads with extended contours
Lead-in layers inseparably applied to the semiconductor body: for devices consisting of semiconductor layers on insulating or semi-insulating substrates
Materials
Bond pads
Bump connectors
consisting of soldered or bonded constructions
References relevant to classification in this group
This subclass/group does not cover:
Bump connectors
Lead-frames or other flat leads
References relevant to classification in this group
This subclass/group does not cover:
Leads on insulating substrates
Informative references
Attention is drawn to the following places, which may be of interest for search:
Interconnections between components using lead-frames
an insulative substrate being used as a die pad, e.g. ceramic, plastic
References relevant to classification in this group
This subclass/group does not cover:
Lead-frames with additional leads being a wiring board
Deformation absorbing parts in the lead frame plane, e.g. meanderline shape
References relevant to classification in this group
This subclass/group does not cover:
Lead-frames: geometry for devices being provided for in H01L 29/00
Cross section geometry
References relevant to classification in this group
This subclass/group does not cover:
Lead-frames: geometry for devices being provided for in H01L 29/00
consisting of thin flexible metallic tape with or without a film carrier
References relevant to classification in this group
This subclass/group does not cover:
Thin flexible metallic tape with or without a film carrier provided in the context of subject-matter covered by groups H01L 23/49503 to H01L 23/49568 and H01L 23/49575 to H01L 23/49579
Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
Informative references
Attention is drawn to the following places, which may be of interest for search:
Shape of the substrate
Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
References relevant to classification in this group
This subclass/group does not cover:
Leads on insulating substrates: via connections through the substrates
Multilayer substrates
Informative references
Attention is drawn to the following places, which may be of interest for search:
Multilayer metallisation on monolayer substrate
Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
References relevant to classification in this group
This subclass/group does not cover:
Leads on insulating substrates: multilayer substrates
Leads on insulating substrates: consisting of a plurality of insulating substrates
Leads on insulating substrates: flexible insulating substrates
Leads on insulating substrates: lead-frames fixed on or encapsulated in insulating substrates
Flexible insulating substrates
References relevant to classification in this group
This subclass/group does not cover:
Lead-frames consisting of thin flexible metallic tape with or without a film carrier
Leads on insulating substrates: for flat-cards, e.g. credit cards
for flat-cards, e.g. credit cards
Informative references
Attention is drawn to the following places, which may be of interest for search:
Cards per se
Lead-frames fixed on or encapsulated in insulating substrates
References relevant to classification in this group
This subclass/group does not cover:
Leads on insulating substrates: the leads being also applied on the sidewalls or the bottom of the substrate
Leads on insulating substrates: flexible insulating substrates
characterised by the materials
Informative references
Attention is drawn to the following places, which may be of interest for search:
Materials of the substrates
Materials of the lead-frames
Conductive materials for PCBs
H05K/09D
Carbon, e.g. fullerenes
Informative references
Attention is drawn to the following places, which may be of interest for search:
Superconducting fullerenes
the conductive materials containing organic materials or pastes, e.g. for thick films
Informative references
Attention is drawn to the following places, which may be of interest for search:
For printed circuits
for integrated circuit devices, e.g. power bus, number of leads (to take precedence)
References relevant to classification in this group
This subclass/group does not cover:
Arrangements for conducting electric current to or from the solid state body in operation: lead-in layers inseparably applied to the semiconductor body
Leads on insulating substrates
Capacitive arrangements or effects of, or between wiring layers
Informative references
Attention is drawn to the following places, which may be of interest for search:
Other capacitive arrangements
Inductive arrangements or effects of, or between, wiring layers
Informative references
Attention is drawn to the following places, which may be of interest for search:
Other inductive arrangements
Resistive arrangements or effects of, or between, wiring layers
Informative references
Attention is drawn to the following places, which may be of interest for search:
Other resistive arrangements
Geometry or layout of the interconnection structure
References relevant to classification in this group
This subclass/group does not cover:
Devices consisting of a plurality of semiconductor or other solid state components formed in or on a common substrate: geometrical layout of the components
Informative references
Attention is drawn to the following places, which may be of interest for search:
Algorithms, e.g. computer aided design of layouts of integrated circuits
based on metals, e.g. alloys, metal silicides
References relevant to classification in this group
This subclass/group does not cover:
Arrangements for conducting electric current within the device in operation from one component to another: containing superconducting materials
containing carbon, e.g. fullerenes
Informative references
Attention is drawn to the following places, which may be of interest for search:
Superconducting fullerenes
Nanosized carbon materials per se
including internal interconnections, e.g. cross-under constructions
Informative references
Attention is drawn to the following places, which may be of interest for search:
Internal lead connections
the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
References relevant to classification in this group
This subclass/group does not cover:
Printed circuits; casings or constructional details of electric apparatus; manufacture of assemblages of electrical components
Informative references
Attention is drawn to the following places, which may be of interest for search:
Manufacture or treatment
Mountings per se
Materials
Multilayer substrates
References relevant to classification in this group
This subclass/group does not cover:
Interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates: assembly of a plurality of insulating substrates
Informative references
Attention is drawn to the following places, which may be of interest for search:
Multilayer metallisation on monolayer substrates
Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
References relevant to classification in this group
This subclass/group does not cover:
Interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates: multilayer substrates
Interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates: assembly of a plurality of insulating substrates
Informative references
Attention is drawn to the following places, which may be of interest for search:
Pins attached to insulating substrates
Flexible insulating substrates
References relevant to classification in this group
This subclass/group does not cover:
Interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates: for flat cards, e.g. credit cards
for flat cards, e.g. credit cards
Informative references
Attention is drawn to the following places, which may be of interest for search:
Cards per se
Marks applied to semiconductor devices or parts, e.g. registration marks, test patterns, alignment structures, wafer maps
Definition statement
This subclass/group covers:

Marks for identification purposes, including electrical structures used to generate identification information for electrical read out.

Typical views of marks of this type:

Informative references
Attention is drawn to the following places, which may be of interest for search:
Marking devices, scribers
Marking methods
Marks used for overlay monitoring in photolithography
G03F7/20T22
Alignment marks used in photolithographic machines
G03F9/00T20
Protection against radiation, e.g. light or electromagnetic waves
Definition statement
This subclass/group covers:

Electromagnetic shielding arrangements; RF interference suppression.

Informative references
Attention is drawn to the following places, which may be of interest for search:
Electrostatic shielding in general
Screening of apparatuses or components of PCB
Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
References relevant to classification in this group
This subclass/group does not cover:
Lead-frames: battery in combination with a lead-frame
Lead-frames: oscillators in combination with a lead-frame
comprising conductive layers or plates or strips or rods or rings
Definition statement
This subclass/group covers:

Active and passive measures to prevent or detect tampering; reverse engineering protection structures; seal rings, protection against delamination of layers during dicing

References relevant to classification in this group
This subclass/group does not cover:
Protection against electrostatic charges or discharges
Protection against overvoltage
Impedance arrangements
High-frequency adaptations
Informative references
Attention is drawn to the following places, which may be of interest for search:
Secure housings for data carriers (memories)
G06F21/00N1T
Protective means for data carriers (memories)
Protection against electrostatic charges or discharges, e.g. Faraday shields
Informative references
Attention is drawn to the following places, which may be of interest for search:
Protection against electrostatic discharge (ESD) provided in a semiconductor body
Faraday shields in general
Capacitive arrangements
References relevant to classification in this group
This subclass/group does not cover:
Lead-frames: capacitor integral with or on the lead-frame
Impedance arrangements: inductive arrangements
Impedance arrangements: resistive arrangements
High-frequency adaptations
Informative references
Attention is drawn to the following places, which may be of interest for search:
Capacitive effects between wiring layers on the semiconductor body
Inductive arrangements
References relevant to classification in this group
This subclass/group does not cover:
Impedance arrangements: resistive arrangements
High-frequency adaptations
Informative references
Attention is drawn to the following places, which may be of interest for search:
Inductors formed within interconnection layers
Resistive arrangements
References relevant to classification in this group
This subclass/group does not cover:
Protection against overvoltage
High-frequency adaptations
Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods related thereto
Definition statement
This subclass/group covers:

Examples of first level interconnects

1 = H01L 24/10 and subgroups,

2 = H01L 24/26 and subgroups,

3 = H01L 24/26 and subgroups,

4 = H01L 24/42 and subgroups

References relevant to classification in this group
This subclass/group does not cover:
Manufacture or treatment of parts
Assemblies of semiconductor devices
Applying interconnections to be used for carrying current between separate components within a device
Containers or seals
Mountings
Arrangements for cooling, heating, ventilating or temperature compensation
Arrangements for conducting electric current
Structural electrical arrangements
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
Details of semiconductor bodies or electrodes of semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier
Details peculiar to semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
Details peculiar to semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission
Details peculiar to thermoelectric devices comprising a junction of dissimilar materials
Details peculiar to thermoelectric devices without a junction of dissimilar materials or of thermomagnetic devices
Details peculiar to devices using superconductivity
Details peculiar to piezo-electric, electrostrictive, magnetostrictive devices in general
Details peculiar to devices using galvano-magnetic or similar magnetic effects
Details peculiar to solid state devices adapted for rectifying, amplifying, oscillating or switching without a potential-jump barrier or surface barrier or of Ovshinsky-effect devices
Details peculiar to bulk negative resistance effect devices
Details peculiar to solid state devices not provided for in groups H01L 27/00 to H01L 47/00 and H01L 51/00 and not provided for in any other subclass
Details peculiar to solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part
Printed circuits
Apparatus or manufacturing processes for printed circuits
Special rules of classification within this group

The use of Indexing Codes of the indexing schemes H01L 24/00 and subgroups, H01L 2224/00 and subgroups and H01L 2924/00 and subgroups is mandatory.

Bonding areas; Manufacturing methods related thereto
Definition statement
This subclass/group covers:

Informative references
Attention is drawn to the following places, which may be of interest for search:
Bonding areas on insulating substrates, e.g. chip carriers
Special rules of classification within this group

The following figures show some key technologies relating to H01L 24/00

[N: of a plurality of bonding areas]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Physical circuit design
Glossary of terms
In this subclass/group, the following terms (or expressions) are used with the meaning indicated:

Bump connectors; Manufacturing methods related thereto
Informative references
Attention is drawn to the following places, which may be of interest for search:
Bumps on insulating substrates, e.g. chip carriers
Manufacturing methods for bumps on insulating substrates; Manufacturing methods related thereto
Definition statement
This subclass/group covers:

Informative references
Attention is drawn to the following places, which may be of interest for search:
Manufacturing methods for bumps on insulating substrates
Inks, e.g. metallic inks
[N: Structure, shape, material or disposition of the bump connectors prior to the connecting process]
Definition statement
This subclass/group covers:

[N: of a plurality of bump connectors]
Definition statement
This subclass/group covers:

High density interconnect [HDI] connectors; Manufacturing methods related thereto
Informative references
Attention is drawn to the following places, which may be of interest for search:
Interconnection structure between a plurality of semiconductor chips
[N: Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto]
Definition statement
This subclass/group covers:

Informative references
Attention is drawn to the following places, which may be of interest for search:
metal powder in organic matrix
[N: Manufacturing methods]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Applying adhesive films using preforms
Applying fluids in general
[N: Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto]
Definition statement
This subclass/group covers:

Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Informative references
Attention is drawn to the following places, which may be of interest for search:
Flexible insulating substrates
Thin flexible metallic tape with or without a film carrier
Means for bonding not being attached to, or not being formed on, the body surface to be connected
Informative references
Attention is drawn to the following places, which may be of interest for search:
Holders for supporting the complete device in operation H01L 23/32
[N: Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected]
Definition statement
This subclass/group covers:

by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
Definition statement
This subclass/group covers:

Informative references
Attention is drawn to the following places, which may be of interest for search:
Interconnection structure between a plurality of semiconductor chips
using a wire connector
Informative references
Attention is drawn to the following places, which may be of interest for search:
Wire bonding in general
[N: Batch processes]
Definition statement
This subclass/group covers:

[N: the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting]
Definition statement
This subclass/group covers:

Assemblies consisting of a plurality of individual semiconductor or other solid state devices
Definition statement
This subclass/group covers:

Assemblies consisting of a plurality of individual semiconductor or other solid state devices

References relevant to classification in this main group
This subclass/group does not cover:
Assemblies of photo electrochemical cells, e.g. dye sensitised solar cells
Assemblies of semiconductor devices on lead-frames
Devices consisting of a plurality of semiconductor or other solid state components formed in or on a common substrate
Assemblies of photoelectric cells
Tandem solar cells, meaning monolithically integrated solar cells with different wavelengths sensibilities deposited on one another by coating processes
Generators using solar cells or solar panels
Details of assemblies of electrical components in general
Details of complete circuit assemblies provided for in another subclass
see relevant subclass
Informative references
Attention is drawn to the following places, which may be of interest for search:
Couplings of light guides with optoelectronic elements
Leads on insulating substrates (chip carriers)
Interconnection structures for a plurality of bare semiconductor chips provided on or in an insulating substrate
Arrangements for connecting or disconnecting semi​conductor or solid-state bodies; methods related thereto
Integrated photodetecting devices on a substrate
Integration of organic light emitting devices (OLEDs), e.g. OLED displays
Light sensitive devices structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, and electrically or optically coupled thereto (e.g. opto-couplers)
Organic light emitting devices [OLEDs]
Details of television receivers
Special rules of classification within this main group

The use of Indexing Codes of the indexing scheme H01L 2925/00 for details related to assemblies consisting of a plurality of individual semiconductor or other solid state devices, which are covered by the group H01L 25/00 but not provided for in its subgroups, is mandatory

all the devices being of a type provided for in the same subgroup of groups H01L 27/00 to H01L 51/00
Definition statement
This subclass/group covers:
  • "package in package" devices
  • assemblies of rectifier diodes
the devices being of a type provided for in group H01L 31/00
Special rules of classification within this group

This group is not used (see subgroups).

the devices being arranged next to each other
Definition statement
This subclass/group covers:

Arrays of photodetectors disposed next to one another on a common substrate.

References relevant to classification in this group
This subclass/group does not cover:
Multicolour imagers having a stacked pixel-element structure
Multispectral infra-red imagers, having a stacked pixel-element structure
Assemblies of thin film solar cells
Informative references
Attention is drawn to the following places, which may be of interest for search:
Mechanically stacked solar cells
Glossary of terms
In this subclass/group, the following terms (or expressions) are used with the meaning indicated:
Disposed
means that photodetectors already manufactured are individually placed on the common substrate, as opposed to "integrated" which means the devices are all formed on or in said substrate during the same process
Stacked arrangements of devices
Definition statement
This subclass/group covers:

Photodetectors mechanically stacked on one another:

the devices being solar cells
Definition statement
This subclass/group covers:

Solar cells, normally absorbing different wavelengths, mechanically stacked on one another.

Example:

WO93/21662

the devices being of a type provided for in group H01L 51/42
Definition statement
This subclass/group covers:

Mechanically stacked organic solar cells

Example:

EP1603169

References relevant to classification in this group
This subclass/group does not cover:
Devices consisting of a plurality of light sensitive organic semiconductor components, e.g. organic thin film solar cells, formed in or on a common substrate
Informative references
Attention is drawn to the following places, which may be of interest for search:
Organic light sensitive devices
the devices being of a type provided for in group H01L 51/50
Definition statement
This subclass/group covers:

Assemblies consisting of a plurality of devices specially adapted for light emission and using organic materials as the active part, e.g. assembly of OLEDs.

Examples:

US2006/0244374

EP1466371

US5965907

References relevant to classification in this group
This subclass/group does not cover:
Tiled displays
Informative references
Attention is drawn to the following places, which may be of interest for search:
Electric lamps using LEDs
F21K99/00S
OLEDs electrically connected in parallel
OLEDs electrically connected in series
Stacked OLEDs
Dual displays
the devices being of a type provided for in group H01L 33/00
Informative references
Attention is drawn to the following places, which may be of interest for search:
Electric lamps using LEDs
F21K99/00S
the devices being of types provided for in two or more different main groups of H01L 27/00 to H01L 51/00
Definition statement
This subclass/group covers:

Hybrid modules of active and passive components

References relevant to classification in this group
This subclass/group does not cover:
Interconnections for hybrid circuits
the devices being of types provided for in two or more different subgroups of the same main group of groups H01L 27/00 to H01L 51/00
Definition statement
This subclass/group covers:

Arrangement of memory and logic chips

Arrangement of diode and IGBT

References relevant to classification in this group
This subclass/group does not cover:
Devices consisting of a plurality of semiconductor or other solid state components formed in or on a common substrate and controlled by radiation
Devices consisting of a plurality of semiconductor or other solid state components formed in or on a common substrate.
Definition statementThis main group covers:
This subclass/group covers:

Semiconductor devices consisting of a plurality of semiconductor or other solid state components formed in or on a common substrate, i. e. integrated circuits.

Examples of integrated circuits are: memory arrays (SRAM, DRAM, MRAM, ROM, PROM, EPROM, EEPROM), image sensors (CMOS-type image sensors, CCD-type image sensors), organic and inorganic light emitting diode (LED, OLED) displays, logic integrated circuits, switching integrated circuits, arrangements of active or passive semiconducting components in or on a common substrate, electrostatic discharge (ESD) protection integrated circuits.

This main group covers the following areas:

Semiconductor devices formed in or on a common substrate including only passive thin-film or thick-film components.

Semiconductor devices formed in or on a common substrate including inorganic semiconductor components adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier, e.g. memory arrays.

Semiconductor devices formed in or on a common substrate including inorganic semiconductor components sensitive to electromagnetic radiation, e.g. imagers.

Semiconductor devices formed in or on a common substrate including inorganic semiconductor components having at least one potential-jump barrier or surface barrier and adapted for light emission, e.g. LED arrays.

Semiconductor devices formed in or on a common substrate including thermoelectric or thermomagnetic components.

Semiconductor devices formed in or on a common substrate including components exhibiting superconductivity.

Semiconductor devices formed in or on a common substrate including piezo-electric, electrostrictive or magnetostrictive components.

Semiconductor devices formed in or on a common substrate including components using galvano-magnetic effects or similar magnetic field effects.

Semiconductor devices formed in or on a common substrate including solid state components for rectifying, amplifying or switching without a potential-jump barrier or surface barrier.

Semiconductor devices formed in or on a common substrate including bulk negative resistance effect components.

Semiconductor devices formed in or on a common substrate including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part, e.g. OLED displays, OTFT arrays, OPV modules.

Example:

Relationship between large subject matter areas

Only the physical structure of integrated circuits is covered by H01L 27/00. Electrical circuit arrangements are classified elsewhere. For instance, electrical circuit arrangements for driving OLED displays are covered by G09G 3/3208. Electrical circuit arrangements for driving semiconductor imagers are covered by H04N 5/335.

Examples:

References relevant to classification in this main group
This subclass/group does not cover:
Processes or apparatus specially adapted for the manufacture or treatment of integrated circuits or of parts thereof
Details of integrated circuits
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
Printed circuits
Informative references
Attention is drawn to the following places, which may be of interest for search:
Components for integrated circuits
Processes or apparatus specially adapted for the manufacture or treatment of OLED displays
Processes or apparatus specially adapted for the manufacture or treatment of organic semiconductor integrated devices
Encapsulations specially adapted for OLED displays
Digital stores
Liquid crystal displays
Field emission displays
Plasma display panels
Light sources with substantially two-dimensional radiating surfaces
Electric lamps using semiconductor devices as light generating elements
F21K99/00S
Control circuits for electroluminescent panels based on semiconductive elements, e.g. LEDs
Computer‑aided physical circuit design, e.g. layout for integrated circuits
Measuring electrical variables
Measuring X-radiation, gamma radiation, corpuscular radiation, or cosmic radiation
Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
Electronic switching or gating
Logic circuits, inverting circuits
Light guides
Circuit arrangements for driving OLED displays
Circuit arrangements for driving semiconductor imagers
Bolometers
Coatings
Alloys
Optical filters
Lenses
Photonic crystals
Polarisers
Light sources
Semiconductor Lasers
Touch screens
Special rules of classification within this main group

Only monolithically integrated devices are covered by main group H01L 27/00, in contrast to assemblies consisting of a plurality of individual semiconductor or other solid state devices which are covered by main group H01L 25/00.

In this main group, in the absence of an indication to the contrary, classification is made in the last appropriate place.

In this main group the use of Indexing Code-codes is mandatory to classify additional information. Keywords are assigned to define the invention whenever no appropriate group symbol is available, as well as to define further relevant aspects of the invention.

In this main group the circulation of documents to other related fields is mandatory, whenever appropriate.

Glossary of terms
In this subclass/group, the following terms (or expressions) are used with the meaning indicated:

In this main group, the following terms (or expressions) are used with the meaning indicated:

Passive semiconductor component:
semiconductor component not introducing energy into the integrated circuit where they are integrated. Examples thereof are resistors, capacitors, inductors.
Active semiconductor component:
semiconductor component introducing energy into the integrated circuit where they are integrated. Examples thereof are transistors, diodes, and thyristors.
SOI (Semiconductor on insulator):
Thin monocrystalline semiconductor layer bonded to a support substrate by means of an intermediate insulating layer. Generally a very thin silicon wafer is molecular-bonded to a support substrate by means of a SiO2 layer.
CMOS structure:
Complementary metal oxide semiconductor structure comprising a PMOSFET and an NMOSFET connected the following way.

Example:

Their sharp I-V curve results in low power consumption. They are used as inverters.

Static random‑access memory (SRAM): semiconductor memory wherein each bit of data is stored on four transistors that form two cross‑coupled inverters.

It does not need to be refreshed periodically (static).

Example:

Dynamic random‑access memory (DRAM): semiconductor memory wherein each bit of data is stored in a separate capacitor.

In general it comprises a transistor and a capacitor.

The information fades unless the capacitor charge is refreshed periodically (dynamic).

Example:

US-A-3 387 286

EEPROM: Electrically erasable programmable read only memory.

It generally comprises a select transistor and a memory cell being a MOSFET transistor having a double gate: a floating gate for charge accumulation and state determination, and a control gate, capacitively coupled to the floating gate to determine its state.

Example:

Synonyms and Keywords
IC
Integrated circuit
SITL structure
Static induction transistor logic structure
VLSI
Very Large Scale Integration
I2L structure
Integrated injection logic structure
RAM
Random access memory
SRAM
Static random access memory
DRAM
Dynamic random access memory
FerriRAM, FeRAM
ferroelectric RAM
MRAM
magnetic RAM
ROM
Read only memory
PROM
Programmable read only memory
EPROM
Electrically programmable read only memory
EEPROM
Electrically erasable programmable read only memory
APS
Active pixel sensor
ReRAM, RRAM
resistance random access memory
PRAM, PCRAM
phase-change memory
PPS
Passive pixel sensor
CMOS
Complementary metal oxide semiconductor
CCD imager
Charge coupled device imager
OLED display
Organic light emitting diode display
TOLED display
Transparent OLED display
AMOLED display
Active matrix OLED display
PMOLED display
Passive matrix OLED display
OTFT array
Organic thin film transistor array
TFT array
Thin film transistor array
SOI
Semiconductor on insulator
CCM
Colour changing medium
Devices consisting of a plurality of semiconductor or other solid state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
Definition statement
This subclass/group covers:

Integration of only passive components such as resistors, inductors, capacitors

Informative references
Attention is drawn to the following places, which may be of interest for search:
Passive components as such
Integration of passive components with components specially adapted for rectifying, oscillating, amplifying or switching on a substrate being an insulating body (e.g. SOI):
[N: Thick-film circuits]
Definition statement
This subclass/group covers:

Devices formed in a bulk semiconductor substrate

[N: Thin-film circuits]
Definition statement
This subclass/group covers:

Devices formed on a substrate by thin-film technology.

Devices consisting of a plurality of semiconductor or other solid state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier.
Definition statement
This subclass/group covers:

Integration of active and passive components

Reverse Engineering

[N: Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique]
References relevant to classification in this group
This subclass/group does not cover:
Computer‑aided physical circuit design, e.g. layout for integrated circuits
Master slice integrated circuits
[N: Particular design considerations adapted for requirements of temperature]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Cooling arrangements per se
[N: Charge pumping, substrate bias generation structures]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Circuits therefor
[N: Charge injection in static induction transistor logic structures, i.e. SITL]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Circuits therefor
[N: Integrated injection logic structures, i.e. I2L]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Circuits therefor
[N: Particular design considerations adapted for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection]
Definition statement
This subclass/group covers:

Integration aspects of protecting structures, directed to increase the reliability of integrated circuits, e.g. integrated device arrangements protecting against over-voltage damages, against over-current damages, against thermal runaway, ESD protections, EOS protections .

Informative references
Attention is drawn to the following places, which may be of interest for search:
Emergency protective circuit arrangements
Circuit arrangements for protecting electronic switches
Circuit arrangements for protecting logic circuits
Circuit arrangements for protecting amplifiers
Protection arrangements not implemented within the integrated circuit, e.g. protections at packaging level, at printed circuit board level, or at the system level.
Components per se, including components used as protecting elements
Glossary of terms
In this subclass/group, the following terms (or expressions) are used with the meaning indicated:
IC
Integrated Circuit
ESD
Electro Static Discharge
EOS
Electrical Over-Stress
SOA
Safe Operating Area
[N: Particular design considerations adapted for electrical or thermal protection for MOS devices]
Definition statement
This subclass/group covers:

Integration aspects of protecting device arrangements, wherein the device to be protected includes at least a MOS device.

Informative references
Attention is drawn to the following places, which may be of interest for search:
Latch-up prevention in CMOS
[N: Particular design considerations adapted for electrical or thermal protection for MOS devices using diodes as protective elements]
Definition statement
This subclass/group covers:

Integration aspects of protecting diodes

Informative references
Attention is drawn to the following places, which may be of interest for search:

Attention is drawn to the following places, which may be of interest for search

Diodes per se
Multistep processes for the fabrication of diodes
H01L21/329
IC including a plurality of component not having an active region in common
IC including a plurality of component not having an active region in common
Structural association of diodes and LDMOS
Structural association of diodes and VDMOS
Using diode connected field effect transistors
Using diode connected bipolar transistors
[N: Particular design considerations adapted for electrical or thermal protection for MOS devices using bipolar transistors as protective elements]
Definition statement
This subclass/group covers:

Integration aspects of protecting structures including bipolar transistors, and of the biasing arrangements which render structures adapted to be used as protecting elements

Informative references
Attention is drawn to the following places, which may be of interest for search:

Attention is drawn to the following places, which may be of interest for search

Bipolar transistors per se
Multistep processes for the fabrication of bipolar transistors
H01L21/331
[N: Particular design considerations adapted for electrical or thermal protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistor has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices.]
Definition statement
This subclass/group covers:

Integration aspects of protecting silicon controlled rectifiers, and of their triggering structures.

Example: (from EP 2246885 A1)

Informative references
Attention is drawn to the following places, which may be of interest for search:
Latch-up prevention in CMOS
Thyristors per se
Multistep processes for the fabrication of thyristors
H01L21/332
[N: Particular design considerations adapted for electrical or thermal protection for MOS devices using field effect transistors as protective elements]
Definition statement
This subclass/group covers:

Integration aspects of protecting field effect transistors, and of the triggering structures which render said field effect transistors adapted to be used as protecting elements

Informative references
Attention is drawn to the following places, which may be of interest for search:
Field effect transistors per se
Multistep processes for the fabrication of field effect transistors
H01L21/335
Voltage or current sensing structures in VDMOS
Voltage or current sensing structures in LDMOS
[N: Particular design considerations adapted for electrical or thermal protection for MOS devices using field effect transistors as protective elements and specially adapted to provide an electrical current path other than the field effect induced current path]
Definition statement
This subclass/group covers:

Integration aspects of structural adaptations of the field effect transistors which make them electrically behave in a way which substantially differs from the usual one; modifications aimed to enhance parasitic effects, e.g. the bipolar transistor inherently present in MOS transistors.

Example:

[N: involving a parasitic bipolar transistor triggered by the local electrical biasing of the layer acting as base of said parasitic bipolar transistor]
Definition statement
This subclass/group covers:

Integration details concerning the doping profile, the shape, the structure, the dimensioning of the layer acting as base of the bipolar transistor and of its contact region

Example:

Informative references
Attention is drawn to the following places, which may be of interest for search:
Prevention of punch-through
Prevention of bipolar effect
[N: Particular design considerations adapted for electrical or thermal protection for MOS devices using as protective elements field effect transistor in a "Darlington-like" configuration]
Definition statement
This subclass/group covers:

Integration of an active clamp by means of a field effect transistor, which is driven in a conducting state by a further field effect transistor coupled to its gate electrode.

Example:

References relevant to classification in this group
This subclass/group does not cover:
Active clamps driven by an inverter
[N: Bias arrangement for gate electrode of field effect transistors, e.g. RC networks, voltage partitioning circuits]
Definition statement
This subclass/group covers:

Integration of an active clamp by means of a field effect transistor, which is driven in a conducting state by a RC discriminating circuit or by other voltage partitioning circuits.

References relevant to classification in this group
This subclass/group does not cover:
Field-effect transistors in a "Darlington-like" configuration as protective elements
[N: Particular design considerations adapted for electrical or thermal protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps.]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Resistors or capacitors per se
Multistep processes for the fabrication of resistors, capacitors, inductors
H01L21/329C, H01L21/334C, H01L 28/00
Structural details of fuses
Impedance arrangements
[N: Particular design considerations adapted for electrical or thermal protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses.]
Definition statement
This subclass/group covers:

Details concerning the electrical interconnections between the protecting structures and/or the connections between the protecting structures and the circuit to be protected; specific routing schemes or the provision of dedicated conducting path for the triggering of the protecting structures as well as for the evacuation of the discharge current.

Example:

Informative references
Attention is drawn to the following places, which may be of interest for search:
Interconnections
Routing algorithms
Glossary of terms
In this subclass/group, the following terms (or expressions) are used with the meaning indicated:
ESD buses
conductive traces dedicated to the evacuation of current produced by an electrostatic discharge, or to the propagation of triggering signal for the protecting elements
[N: Particular design considerations adapted for electrical or thermal protection for MOS devices involving a specific disposition of the protective devices]
Definition statement
This subclass/group covers:

Integration of the protecting devices in specific areas of the integrated circuit, such as under the bonding pads, or within the scribe-lines, in peripheral regions of memories or TFT displays, in the substrate region below the insulator layer of SOI wafers.

Informative references
Attention is drawn to the following places, which may be of interest for search:
Hybrid SOI
IC having three dimensional layout
Arrangements to prevent high voltage or static electricity failures in active matrix liquid crystal display cells
[N: integrated circuits having a two-dimensional layout of components without a common active region]
[N: comprising components of the field-effect type
References relevant to classification in this group
This subclass/group does not cover:
Electrical or thermal protection for MOS devices
including a plurality of individual components in a repetitive configuration
Definition statement
This subclass/group covers:

Cross-point memories using a fuse or anti-fuse as the active element.

[N: including resistors or capacitors only]
Definition statement
This subclass/group covers:

Cross-point memories

[N: including diodes only]
Definition statement
This subclass/group covers:

Cross-point memories in which a diode is the selection element.

[N: Bipolar dynamic random access memory structures
Informative references
Attention is drawn to the following places, which may be of interest for search:
[N: Static bipolar memory cell structures
Informative references
Attention is drawn to the following places, which may be of interest for search:
Circuits
[N: Bipolar electrically programmable memory structures
Informative references
Attention is drawn to the following places, which may be of interest for search:
Using fuses
including field-effect components
Definition statement
This subclass/group covers:

Integration of memories (e.g. SRAM, ROM, PROM) with peripheral circuits.

References relevant to classification in this group
This subclass/group does not cover:
Integration of DRAM memories with peripheral circuits
Integration of FeRAM memories with peripheral circuits
Integration of floating-gate memories with peripheral circuits
Integration of nitride-based memories (e.g. NROM, MONOS, SONOS) with peripheral circuits
Dynamic random access memory structures
Definition statement
This subclass/group covers:

Dynamic random access memory structures and corresponding multistep manufacturing methods.

References relevant to classification in this group
This subclass/group does not cover:
Bipolar DRAMs
H01L27/105T2
Informative references
Attention is drawn to the following places, which may be of interest for search:
Circuits
G11C1/24, G11C 11/401
Special rules of classification within this group

In this group and its groups the last place rule is not used and multi-aspect classification is used, i.e. classification is made in any appropriate place.

[N: comprising floating-body transistors, e.g. floating-body cells]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Floating-body transistors per se
[N: with one-transistor one-capacitor memory cells]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Capacitors for integrated circuits per se
[N: the transistor having a trench structure in the substrate]
References relevant to classification in this group
This subclass/group does not cover:
One-transistor one-capacitor cells in which both the transistor and the capacitor are in one substrate trench
[N: the transistor being of the FinFET type]
Informative references
Attention is drawn to the following places, which may be of interest for search:
FinFETs per se
[N: the capacitor being in a substrate trench]
References relevant to classification in this group
This subclass/group does not cover:
One-transistor one-capacitor cells in which both the transistor and the capacitor are in one substrate trench
Informative references
Attention is drawn to the following places, which may be of interest for search:
Conductor-insulator-semiconductor capacitors (e.g. formed in a substrate trench) per se
H01L21/334C, H01L 29/92
[N: Multistep manufacturing methods]
References relevant to classification in this group
This subclass/group does not cover:
Manufacturing methods for DRAM cells based on floating-body transistors
[N: with at least one step of making the capacitor or connections thereto]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Making the capacitor per se
H01L 28/40, H01L21/334C
[N: with at least one step of making the trench]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Making the capacitor per se
H01L21/334C
[N: with at least one step of making the transistor]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Making the transistor per se
H01L21/335
[N: the transistor having a trench structure in the substrate]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Vertical transistor in combination with a capacitor formed in a substrate trench
[N: the transistor being of the FinFET type]
Informative references
Attention is drawn to the following places, which may be of interest for search:
FinFETs per se
[N: with at least one step of making a bit line contact]
References relevant to classification in this group
This subclass/group does not cover:
Integration of SRAM memories with peripheral circuits
Informative references
Attention is drawn to the following places, which may be of interest for search:
Making contacts per se
Circuits
Static random access memory structures [N: and multistep manufacturing processes therefor (circuits G11C 11/40)]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Manufacture of resistors per se
circuits
[N: Read-only memory structures]
Definition statement
This subclass/group covers:

ROM (e.g. mask ROM) and PROM (e.g. memory cells comprising a field-effect transistor and a fuse or anti-fuse) memories.

References relevant to classification in this group
This subclass/group does not cover:
Integration of ROM or PROM memories with peripheral circuits
Cross-point memories without a field-effect transistor
Informative references
Attention is drawn to the following places, which may be of interest for search:
Circuits and programmation of ROMs and PROMs
[N: Electrically programmable read-only memories]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Circuits and programmation of EEPROMs
[N: with ferroelectric memory capacitor]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Ferroelectric capacitors per se
[N: with floating gate]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Floating-gate transistors per se
Special rules of classification within this group

In groups H01L 27/11517 to H01L 27/1156, in the absence of indication to the contrary, an invention is classified in the last appropriate place.

[N: with charge trapping gate insulator, e.g. MNOS, NROM]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Memory transistors in which the charge is stored in an insulating charge-trapping layer per se
[N: with gate electrode comprising a layer which is used for its ferroelectric memory properties, e.g. MFS (metal-ferroelectric-semiconductor), MFMIS (metal-ferroelectric-metal-insulator-semiconductor)]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Memory transistors with a ferroelectric layer in the gate stack per se
[N: Masterslice integrated circuits]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Computer‑aided physical circuit design, e.g. layout design for integrated circuits
Special rules of classification within this group

If a layout is shown, the group symbol H01L 27/0207 is also allocated.

the substrate being other than a semiconductor body, e.g. an insulating body
Definition statement
This subclass/group covers:

Integration of TFTs on an insulating or insulator-covered substrate, such as

Glass, plastic, insulator coated metal or other non-semiconducting substrates.

References relevant to classification in this group
This subclass/group does not cover:

Examples of places where the subject-matter of this group is covered when specially adapted, used for a particular purpose, or incorporated in a larger system:

AMOLED displays
Informative references
Attention is drawn to the following places, which may be of interest for search:
Thin film unipolar field-effect transistors, i.e. TFTs, per se
Multistep processes to manufacture TFTs
H01L21/336D
Manufacture of a plurality of TFTs on a non-semiconducting substrate
H01L21/77T
Active matrix LCD displays
Circuit arrangements for AM displays
Glossary of terms
In this subclass/group, the following terms (or expressions) are used with the meaning indicated:
AMLCD display
active matrix liquid crystal display
TFT
Thin film unipolar field-effect transistor
AMOLED display
active matrix organic light emitting diode display
[N: the substrate comprising an insulating body on a semiconductor body, e.g. SOI (three-dimensional layout H01L 27/0688)]
Definition statement
This subclass/group covers:

SOI integrated circuits.

Informative references
Attention is drawn to the following places, which may be of interest for search:
Multistep processes to manufacture monocrystalline silicon TFTs on insulating substrates
H01L21/336D3
Monocrystalline TFTs per se
Multistep processes to manufacture devices on a substrate being other than a semiconductor body
Dielectric regions, such as EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology
[N: combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits]
Definition statement
This subclass/group covers:

Integrated circuits employing partial SOI.

[N: combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET]
Definition statement
This subclass/group covers:

Integrated circuits with FinFETs on an insulating substrate

Informative references
Attention is drawn to the following places, which may be of interest for search:
Arrangements including only transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Arrangements including only CMISFET transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Multistep processes to manufacture transistors with a gate at the side of the channel and a horizontal current flow
H01L21/336S2
Transistors with a gate at the side of the channel and a horizontal current flow
Synonyms and Keywords
FinFET
MuGFET, BarFET, Triple gate FET, OMEGA FET, Pi-Gate FET
[N: using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Crystallisation per se
combined with thin-film or thick-film passive components
Definition statement
This subclass/group covers:

Integrated circuits having TFTs integrated with passive components, e.g. antennas, capacitors

References relevant to classification in this group
This subclass/group does not cover:
Memories employing capacitors, e.g. DRAM
Informative references
Attention is drawn to the following places, which may be of interest for search:
RFID circuits
Storage capacitors associated with the pixel electrode in AMLCD displays
SOI arrangements
Devices consisting of a plurality of semiconductor or other solid state components formed in or on a common substrate including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength, or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation.
Definition statement
This subclass/group covers:

Arrangements of solar cells or other semiconducting energy conversion devices, arrangements of photo-detecting elements such as 2D-detectors, imagers

References relevant to classification in this group
This subclass/group does not cover:
Organic semiconductor radiation detecting components
Informative references
Attention is drawn to the following places, which may be of interest for search:
Radiation-sensitive components structurally associated with one or more electric light sources only
Couplings of light guides with optoelectronic elements
Radiation detecting components
Energy conversion devices
Definition statement
This subclass/group covers:

Integrated device structures comprising an energy conversion device (solar cell) and another solid state electronic device.

This group mostly covers solar cell structures comprising integrated bypass diodes.

This group also covers bypass diodes associated with solar cells but not integrated with it

Examples:

US2003075215 A1

US2010147353A1

Informative references
Attention is drawn to the following places, which may be of interest for search:
Circuitry connections of bypass diodes in solar panel(s)
Solar cell structures
Semiconductor organic solar cells
[N: in a repetitive configuration, e.g. planar multijunction solar cells]
Definition statement
This subclass/group covers:

Solar cells in a planar repetitive configuration on a semiconductor substrate (see EP2328182; EP1936700); Solar cells microarrays

EP1936700

EP2328182

References relevant to classification in this group
This subclass/group does not cover:
Thin film solar cells deposited on a substrate and connected in series by patterning the deposited layers
[N: comprising only thin film solar cells deposited on a substrate]
Definition statement
This subclass/group covers:

Inorganic solar cells thin film technology.

Examples:

EP2246901

EP2224495

References relevant to classification in this group
This subclass/group does not cover:
Solar cells in a planar repetitive configuration on a semiconductor substrate (i.e. not thin-film type)
Informative references
Attention is drawn to the following places, which may be of interest for search:
Details of the substrate, including intermediate (barrier) layers
Details of the substrate, for amorphous silicon devices
Roll to roll deposition of amorphous silicon devices
Method of deposition of CIS compounds
Method of deposition of amorphous silicon cells
I-III-VI compounds (CIS) deposited on a flexible substrate
[N: comprising multiple vertical junction or V-groove junction solar cells formed in a semiconductor substrate]
Definition statement
This subclass/group covers:

Solar cells formed in a semiconductor substrate (bulk type) and being separated by V-grooves or having a plurality of vertical junctions (see EP44396; EP742959; US5494832).

EP044396

EP618623

EP742959

Devices controlled by radiation
Definition statement
This subclass/group covers:

Integration of devices controlled by radiation. These can be for detection purposes, such as photodiode arrays, or for imaging purposes, such as imagers.

Informative references
Attention is drawn to the following places, which may be of interest for search:
Radiation detecting components
Organic semiconductor devices controlled by radiation
[N: with at least one potential jump or surface barrier]
Definition statement
This subclass/group covers:

Example: integration of a visible and an infrared sensor

Special rules of classification within this group

This group is not exclusive with H01L 27/1446

[N: in a repetitive configuration]
Definition statement
This subclass/group covers:

Spatially repeated sensors of the same type such as photodiode arrays, position-sensitive sensors. The repetition can be linear or in form or a matrix, but not for imaging purposes.

Example:

Informative references
Attention is drawn to the following places, which may be of interest for search:
Imaging devices
Special rules of classification within this group

This group is not exclusive with H01L 27/1443.

The spatial repetition should not be for imaging purposes.

Imager structures
Definition statement
This subclass/group covers:

Inorganic semiconductor imaging devices

References relevant to classification in this group
This subclass/group does not cover:
Organic semiconductor imaging devices
Informative references
Attention is drawn to the following places, which may be of interest for search:
Control circuit arrangements for driving solid state imagers
Details of semiconductor imagers (for television systems)
Waveguides
Optical filters
Glossary of terms
In this subclass/group, the following terms (or expressions) are used with the meaning indicated:
Active pixel sensor (APS)
Sensor comprising pixel amplification means, e.g. a transistor as source follower
Aperture ratio
Ratio between light sensitive area of a pixel and the total area occupied by that pixel
Backside illumination
Illumination of the imagers from the of the device where the imager circuitry has not been formed
Blooming
Spilling over of charges from one pixel to the next one after overexposure
Charge coupled device
Architecture of an integrated circuit based on the transport of charge packets by capacitive coupling from one capacitor to the next one
Charge injection device
Architecture of semiconductor device based on measuring currents induced in MOS capacitors at the moment charge packets are injected into the substrate
Dark current
Signal generated by the image sensor when the device is in the dark
Delay line
Component used to delay an electrical signal over a defined time
Dynamic range
Ratio of the largest possible signal (full well capacity of the pixel) divided by the smallest possible signal (background noise) of a sensor-
Frame-transfer CCD
Two dimensional architecture of a CCD imager that has an analogue memory cell for every pixel below the total array of light sensitive pixels
Full-frame CCD
Two dimensional architecture of a CCD imager transferring collected charge directly to readout
Integration time
Time that an imager is collecting charges (photon generated and/or dark current generated)
Interlaced scanning
Scanning mode in which only part (odd or even lines) of the lines of the image are captured in an exposure period
Interline-transfer CCD
Two dimensional architecture of a CCD imager wherein each photodiode has a parallel CCD storage region covered by an opaque mask. After image data has been collected and transferred to the adjacent CCD storage region charge is CCD-shifted vertically to the readout IC.
Overflow drain
Doped region to extract undesired charge resulting from blooming
Passive pixel sensor
Pixels comprising per pixel only a photodiode or a photodiode and an addressing transistor
Photoconductor
Material changing its conductivity when light impinges on it. The delta in conductivity is measured and the incoming radiation calculated in imagers.
TDI-type CCD-imager
Time delay and integration (TDI) is a type of CCD wherein a TDI clock is used to synchronize the movement of charged packets in a CCD with that of another movement.
Wafer level processing
Processing of several semiconductor devices in a single wafer in the same processing cycle
Synonyms and Keywords
APS
Active pixel sensor
CCD
Charge coupled device
PPS
Passive pixel sensor
[N: Structural or functional details thereof]
Definition statement
This subclass/group covers:

This group covers,

Details of organic semiconductor imaging structures such as encapsulations, geometry of disposition of passive and active elements, lenses, isolation, etc, whenever they are specific for semiconductor imaging devices, i.e. they solve problems specific to semiconductor imaging devices.

Informative references
Attention is drawn to the following places, which may be of interest for search:
Encapsulation of integrated circuits
[N: Special geometry or disposition of pixel-elements, address-lines or gate-electrodes]
Definition statement
This subclass/group covers:

The disposition of the elements within the pixel, such as the transfer, driving, reset transistors, capacitor, photodetector. Also covered are the disposition of electrodes and wiring lines such as the power, bit and data lines. Disposition of the different doped regions within the pixel also fall within the scope of the definition of this subclass.

Examples:

US 2011/019063

[N: Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery]
Definition statement
This subclass/group covers:

Example:

[N: Geometry of the photosensitive area]
Definition statement
This subclass/group covers:

Only geometrical issues of the photosensitive area.

US 2010/092875

References relevant to classification in this group
This subclass/group does not cover:
Details of an APS photosensitive area such as doping or depth
[N: Imagers having pixel-elements with integrated switching, control, storage or amplification elements]
Definition statement
This subclass/group covers:

Active pixel sensors [APS], i.e. sensors having in each pixel a photodetecting element and amplifications means within the pixel. Very often CMOS technology is used.

Example:

Informative references
Attention is drawn to the following places, which may be of interest for search:
Scanning details of imagers
Circuitry of imagers
[N: characterised by the photosensitive area]
Definition statement
This subclass/group covers:

An APS wherein the photosensitive area is characterised by its doping, depth, etc.

Example:

US 2011/241089

References relevant to classification in this group
This subclass/group does not cover:
Only geometrical (i.e.. layout) aspects of a photosensitive area in imagers
[N: involving a transistor]
Definition statement
This subclass/group covers:

APS-imagers wherein the invention concerns a specific feature of at least one of the transistor within the unit cell (transfer transistor, reset transistor, source follower, ...).

[N: having a special gate structure]
Definition statement
This subclass/group covers:

Example:

US 2011/241080

[N: characterised by the channel of the transistor, e.g. channel having a doping gradient]
Definition statement
This subclass/group covers:

Example:

US 2011/241079

[N: Containers]
Definition statement
This subclass/group covers:

Encapsulations specially adapted for imagers

Example:

Informative references
Attention is drawn to the following places, which may be of interest for search:
Encapsulation of integrated circuits in general
Containers of integrated circuits in general
[N: Coatings]
Definition statement
This subclass/group covers:

Any kind of coatings within the imager (e.g. interlayer dielectric (ILD), antireflective coatings (ARC)).

Example:

Informative references
Attention is drawn to the following places, which may be of interest for search:
Coatings
Optical filters
[N: Colour filter arrangements]
Definition statement
This subclass/group covers:

Examples:

[N: Optical shielding]
Definition statement
This subclass/group covers:

Examples:

References relevant to classification in this group
Shielding in CCD-type imagers
[N: Optical elements or arrangements associated with the device]
Definition statement
This subclass/group covers:

Optical elements such as lenses, reflectors, light guiding structures within the device.Example:

Informative references
Attention is drawn to the following places, which may be of interest for search:
Lenses
Photonic crystals
[N: Microlenses]
Definition statement
This subclass/group covers:

Example:

[N: Reflectors]
Definition statement
This subclass/group covers:

Elements reflecting light towards the light detecting portion

Example:

[N: Pixel isolation structures]
Definition statement
This subclass/group covers:

Electrical or thermal isolation structures between pixels.

[N: Electrical isolation]
Definition statement
This subclass/group covers:

Electrical isolation structures between pixels such as doped regions, STI.

Example:

WO 2010/90149

[N: Thermal isolation]
Definition statement
This subclass/group covers:

Thermal isolation structures between pixels

Example:

[N: Wafer-level processed structures]
Definition statement
This subclass/group covers:

Structures processed at a wafer level.

Example:

Informative references
Attention is drawn to the following places, which may be of interest for search:
Manufacture thereof
[N: Assemblies, i.e. Hybrid structures]
Definition statement
This subclass/group covers:

Assemblies comprising a substrate having the image sensor connected to another substrate having the circuitry to drive it.

Example:

References relevant to classification in this group
This subclass/group does not cover:
Hybrid-type infrared imagers
Hybrid-type X-ray imagers
Informative references
Attention is drawn to the following places, which may be of interest for search:
Interconnect structures
[N: Interconnect structures]
Definition statement
This subclass/group covers:

Structures to connect e.g. one imaging substrate with its driving substrate, or an image sensor with the external driving circuitry, or special connections within the device.

US 2008/308890

[N: Structures specially adapted for transferring the charges across the imager perpendicular to the imaging plane]
Definition statement
This subclass/group covers:

Imagers having the circuitry beneath the photosensitive area whenever special arrangements are made to transfer the charges from the sensor to the circuitry.

[N: Back illuminated imager structures]
Definition statement
This subclass/group covers:

Imagers wherein light impinges from the surface of the semiconductor wafer opposite to the surface where the imaging structure has been created.

Example:

[N: Electronic components shared by two or more pixel-elements, e.g. one amplifier shared by two pixel elements]
Definition statement
This subclass/group covers:

Components (doped regions, transistors, lines) shared by adjacent pixels.

Example:

[N: Photodiode arrays; MOS imagers]
Definition statement
This subclass/group covers:

Photodiode arrays for imaging purposes and MOS imagers.

[N: Colour imagers]
Definition statement
This subclass/group covers:

Imagers with pixels each for a primary colour, e.g. RGB, e.g. achieved by means of filters.

References relevant to classification in this group
This subclass/group does not cover:
Colour imagers having photoconductive layer
[N: Multicolour imagers having a stacked pixel-element structure, e.g. npn, npnpn or MQW elements]
Definition statement
This subclass/group covers:

Colour imager with stacked configuration, such as a multiple pn-junction stack each to detect a colour.

Example:

[N: Infra-red imagers]
Definition statement
This subclass/group covers:

Imagers for sensing infrared radiation

References relevant to classification in this group
This subclass/group does not cover:
Infrared imagers having photoconductive layer
[N: of the hybrid type]
Definition statement
This subclass/group covers:

Imagers for sensing infrared radiation having an infrared sensor in a substrate and the driving circuitry in a separate substrate both being connected together.

Informative references
Attention is drawn to the following places, which may be of interest for search:
Hybrid type imagers in general
Hybrid type X-ray imagers
Interconnect structures
Infrared imagers having photoconductive layer
[N: Multispectral infra-red imagers, having a stacked pixel-element structure, e.g. npn, npnpn or MQW structures]
Definition statement
This subclass/group covers:

Infrared imagers having generally a stack: LWIR, MWIR, SWIR. The structure is generally similar to that in H01L 27/14647 but for sensing infrared radiation.

Informative references
Attention is drawn to the following places, which may be of interest for search:
Stacked colour imagers
[N: Blooming suppression]
Definition statement
This subclass/group covers:

Structural arrangements to suppress blooming (see glossary of terms in H01L 27/146) such as overflow drains.

Informative references
Attention is drawn to the following places, which may be of interest for search:
Blooming suppression in imagers having photoconductive layer
[N: Overflow drain structures]
Definition statement
This subclass/group covers:

Vertical and horizontal overflow drains

Informative references
Attention is drawn to the following places, which may be of interest for search:
Overflow drains in imagers having photoconductive layer
[N: X-ray, gamma-ray or corpuscular radiation imagers]
Definition statement
This subclass/group covers:

Imagers for sensing X-ray, G-rays or corpuscular radiation

Informative references
Attention is drawn to the following places, which may be of interest for search:
X-ray imagers having photoconductive layer
Measuring X-, gamma- or corpuscular radiation
[N: Direct radiation imaging structures]
Definition statement
This subclass/group covers:

The semiconductor layers convert directly the incoming radiation into charges, without need of a scintillator

[N: of the hybrid type]
Definition statement
This subclass/group covers:

Imagers for sensing X-ray, gamma-ray or corpuscular radiation having an infrared sensor in a substrate and the driving circuitry in a separate substrate both being connected together.

Informative references
Attention is drawn to the following places, which may be of interest for search:
Hybrid type imagers in general
Hybrid type infrared imagers
Interconnect structures
[N: Indirect radiation imagers e.g. using luminescent members]
Definition statement
This subclass/group covers:

This group comprises X-ray radiation imagers having a scintillator (an ionic solid) which converts incoming X-ray radiation into visible light. The detector detects the visible light converted by the scintillator (also called phosphor).

Informative references
Attention is drawn to the following places, which may be of interest for search:
Measuring X-ray radiation with a scintillation-diode combination
[N: Imagers using a photoconductor layer]
Definition statement
This subclass/group covers:

These imagers work on the principle that the photoconductive layer changes its conductivity with the incoming radiation. The change in conductivity is measured and the incoming radiation derived.

[N: Infra-red imagers of the hybrid type]
Definition statement
This subclass/group covers:

Photoconductive imagers having a substrate with the imagers formed therein and another connected thereto with the electronic circuit.

Informative references
Attention is drawn to the following places, which may be of interest for search:
Hybrid type imagers in general
Hybrid type infrared imagers
Hybrid type X-ray imagers
Interconnect structures
[N: Blooming suppression]
References relevant to classification in this group
This subclass/group does not cover:
Blooming suppression in PD- or MOS-imagers
[N: Overflow drain structures]
References relevant to classification in this group
This subclass/group does not cover:
Overflow structures in PD- or MOS-imagers
[N: X-ray, gamma-ray or corpuscular radiation imagers]
References relevant to classification in this group
This subclass/group does not cover:
X-ray detecting PD- or MOS-imagers
Informative references
Attention is drawn to the following places, which may be of interest for search:
Measuring X-, gamma- or corpuscular radiation
[N: Contact-type imagers]
Definition statement
This subclass/group covers:

Imagers having integrated light sources, wherein the light emitted from the integrated light source is reflected on the object to be detected and enters the imagers. Examples thereof are scanning heads, photocopier heads or fingerprint detectors

Informative references
Attention is drawn to the following places, which may be of interest for search:
CID-type CCD-imagers wherein the object to be imaged in contact with the sensor
Fingerprint recognition
Scanning heads
[N: Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof]
Definition statement
This subclass/group covers:

Multistep processes specially adapted for the manufacture of imagers

[N: Process for coatings or optical elements]
Definition statement
This subclass/group covers:

Formation of coatings (antireflective coatings, filters, shielding) as well as micro lenses and other optical elements.

Informative references
Attention is drawn to the following places, which may be of interest for search:
Coatings in general
Optical filters
Lenses
Photonic crystals
Coatings
Optical elements
[N: Wafer level processing]
Definition statement
This subclass/group covers:

Wafer level imager manufacture

Informative references
Attention is drawn to the following places, which may be of interest for search:
Wafer level imagers
[N: MOS based technologies]
Definition statement
This subclass/group covers:

Manufacturing process of imagers using technology of the MOS-type

[N: Assemblies, i.e. hybrid integration]
Definition statement
This subclass/group covers:

Manufacture of hybrid-type imagers.

The manufacture is in general for any kind of hybrid-type imagers (see types below under informative references).

Informative references
Attention is drawn to the following places, which may be of interest for search:
Hybrid-type imagers in general
Hybrid-type infrared imagers
Hybrid-type X-ray imagers
Hybrid-type infrared photoconductive
Charge coupled imagers
Definition statement
This subclass/group covers:

CCD-type imagers

Informative references
Attention is drawn to the following places, which may be of interest for search:
Charge coupled devices per se
[N: Special geometry or disposition of pixel-elements, address lines or gate-electrodes]
Definition statement
This subclass/group covers:

Lines and electrodes layouts, disposition of pixel elements such as the transfer gates, photodetectors of CCD-type imagers.

Informative references
Attention is drawn to the following places, which may be of interest for search:
Circuit arrangements for driving solid state imagers
[N:Optical shielding]
Definition statement
This subclass/group covers:

Shielding specific to CCDs.

Informative references
Attention is drawn to the following places, which may be of interest for search:
Shielding in general for imagers
[N: Containers; Encapsulations]
Definition statement
This subclass/group covers:

Packaging specially adapted for CCD-type imagers.

[N: Coatings]
Definition statement
This subclass/group covers:

Any kind of coatings on the CCD such as antireflective coatings, passivation coatings.

[N: Optical elements or arrangements associated with the device]
Definition statement
This subclass/group covers:

Optical elements in CCD-imagers, e.g. micro lenses, light guiding paths, reflective paths.

[N: Hybrid structures]
Definition statement
This subclass/group covers:

CCD-image sensor in one substrate connected to its driving IC in another substrate.

Informative references
Attention is drawn to the following places, which may be of interest for search:
Hybrid Infrared CCD or CID imagers
[N: Linear CCD imagers]
Definition statement
This subclass/group covers:

CCD-imagers having a linear arrangement of the pixels, e.g. as fax heads or photocopiers

[N: Area CCD imagers]
Definition statement
This subclass/group covers:

Pixels in a 2D matrix form

[N: Frame-interline transfer]
Definition statement
This subclass/group covers:

Combination of interline transfer with a frame transfer (see hereafter).

Each photodiode has a parallel CCD region which shifts charge vertically to a storage 2D matrix (one storage pixel per one photosensitive pixel). The charges stored in the storage matrix are then read out.

Example:

[N: Interline transfer]
Definition statement
This subclass/group covers:

Each photodiode has a parallel CCD storage region covered by an opaque mask. After image data has been collected and transferred to the adjacent CCD storage region charge is CCD-shifted vertically to the readout IC.

[N: Frame transfer]
Definition statement
This subclass/group covers:

The photosensitive 2D array has adjacent a 2D storage area, having a storage pixel per photosensitive pixel. The charges collected are transferred in parallel to the storage area for readout.

Example:

[N: Time-delay and integration]
Definition statement
This subclass/group covers:

Time delay and integration type CCD imager.

[N: CID imagers]
Definition statement
This subclass/group covers:

CID place the object to be imaged in contact with the sensor and use, typically, LEDs for the illumination of the object to be imaged.

Informative references
Attention is drawn to the following places, which may be of interest for search:
Contact-type imagers
including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
Definition statement
This subclass/group covers:

Devices consisting of a plurality of monolithically integrated inorganic semiconductor light emitting diode (LED) components or consisting of inorganic semiconductor LED components monolithically integrated with other semiconductor components.

Informative references
Attention is drawn to the following places, which may be of interest for search:
Printing devices using LED arrays as print heads
LED devices
LED devices with a plurality of light emitting regions
Hybrid assemblies of a plurality of individual LED devices
Hybrid assemblies of LED devices with other semiconductor devices
Displays having an organic semiconductor light emitting material or comprising a mixture of an inorganic and an organic semiconductor light emitting material (OLED displays)
Devices consisting of semiconductor laser diode components monolithically integrated with other components
LCD displays
including thermoelectric components with or without a junction of dissimilar materials; including thermomagnetic components
Definition statement
This subclass/group covers:

This group covers thermoelectric generators using the Seebeck effect to convert heat to electrical energy, thermoelectric coolers using the Peltier effect to create a temperature gradient and the related devices.

Devices monolithically integrating components individually covered by groups H01L 35/00 or H01L 37/00, e.g. Seebeck or Peltier components, either with components of the same kind, e.g. thermocouple arrays, or with components of a different kind, e.g. semiconductor diodes, transistors

Informative references
Attention is drawn to the following places, which may be of interest for search:
Measuring thermal radiation - using thermocouples - using resistors, e.g. bolometers- using capacitors, e.g. pyroelectric sensors
Peltier effect devices only for cooling of semiconductor or other solid state devices
Infrared imagers based on semiconductor devices, e.g. - photodiodes - photoconductors - CCDs- using organic semiconductors
Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat
Thermoelectric devices comprising a junction of dissimilar materials
Generators or motors not provided for elsewhere
Special rules of classification within this group

Classification of relevant details of the individual thermoelectric or thermomagnetic devices such as structure, materials, or manufacturing steps is mandatory and needs to be done in groups H01L 35/00 or H01L 37/00, by allocating at least Indexing Code symbols thereof.

Synonyms and Keywords
TEG
thermoelectric generator
TEC
thermoelectric cooler
TEM
thermoelectric module
ZT
dimensionless figure of merit
including components exhibiting superconductivity
Definition statement
This subclass/group covers:

Devices monolithically integrating components individually covered by main group H01L 39/00, i.e. superconductive components, either with components of the same kind, e.g. Josephson junction arrays, or with components of a different kind, e.g. semiconductor diodes, transistors

Informative references
Attention is drawn to the following places, which may be of interest for search:
Quantum computers
Digital memories
Electronic switching circuits
Logic circuits
Special rules of classification within this group

Classification of relevant details of the individual superconductive devices such as structure, materials, or manufacturing steps is mandatory and needs to be done in group H01L 39/00, by allocating at least Indexing Code symbols thereof.

Synonyms and Keywords
JJ
Josephson junction
RSFQ
Rapid single flux quantum
including piezo-electric components; including electrostrictive components; including magnetostrictive components
Definition statement
This subclass/group covers:

Devices monolithically integrating components individually covered by group H01L 41/00, e.g. piezo-electric [PE] or magnetostrictive [MS] components, either with components of the same kind, e.g. actuator arrays, or with components of a different kind, e.g. semiconductor diodes, transistors

Informative references
Attention is drawn to the following places, which may be of interest for search:
Ultrasonic transducer arrays
Ink-jet print heads
Digital memories, e.g. FRAMs
Special rules of classification within this group

Classification of relevant details of the individual PE or MS devices such as structure, materials, or manufacturing steps is mandatory and needs to be done in group H01L 41/00, by allocating at least Indexing Code symbols thereof.

Synonyms and Keywords
BAW
Bulk acoustic wave
SAW
Surface acoustic wave
MS
Magnetostrictive
PE
Piezoelectric or electrostrictive
including components using galvano-magnetic effects, e.g. Hall effects; using similar magnetic field effects
Definition statement
This subclass/group covers:

Devices monolithically integrating components individually covered by main group H01L 43/00, e.g. magnetoresistive components, either with components of the same kind, e.g. arrays, or with components of a different kind, e.g. semiconductor diodes, transistors

Further classification information:

covers MRAM structures comprising multiple (arrayed) MR components, e.g. bit or word lines arrangements.

covers MRAM structures comprising MR components and two-terminal selection components, e.g. semiconductor diodes, MIM switches.

covers MRAM structures comprising MR components and selection components having more than two terminals, e.g. bipolar transistors.

Informative references
Attention is drawn to the following places, which may be of interest for search:
Measuring magnetic quantities; Magnetometers
Digital memories - using spin effects- using Hall devices
Electronic switching circuits- Logic circuits
Special rules of classification within this group

Classification of relevant details of the individual devices such as structure, materials, or manufacturing steps is mandatory and needs to be done in group H01L 43/00, by allocating at least Indexing Code symbols thereof.

Synonyms and Keywords
GMR
Giant magnetoresistance
MR
Magnetoresistance
MTJ
Magnetic tunnel junctionMR tunnel junction
TMR
Tunnel magnetoresistance
MRAM
Magnetoresistive RAM
including solid state components for rectifying, amplifying or switching without a potential-jump barrier or surface barrier
Definition statement
This subclass/group covers:

Devices monolithically integrating components individually covered by main group H01L 45/00, e.g. bulk switching components, either with components of the same kind, e.g. arrays, or with components of a different kind, e.g. semiconductor diodes, transistors

Informative references
Attention is drawn to the following places, which may be of interest for search:
RRAM digital memories
Dielectric breakdown anti-fuse memories
Resistor or anti-fuse arrays - integrated with junction diodes- integrated with transistors
Devices integrating bulk negative differential resistance components, e.g. Gunn elements
Special rules of classification within this group

Classification of relevant details of the individual bulk switching devices such as structure, materials, or manufacturing steps is mandatory and needs to be done in group H01L 45/00, by allocating at least Indexing Code symbols thereof.

Synonyms and Keywords
CBRAM
Conductive bridging RAM
PCM
Phase change materialPhase change memory
PRAMPCRAM
Phase change RAM
RRAMRERAM
Resistance switching RAM
including bulk negative resistance effect components
Definition statement
This subclass/group covers:

Devices monolithically integrating components individually covered by main group H01L 47/00, e.g. Gunn effect components, either with components of the same kind, e.g. arrays, or with components of a different kind, e.g. semiconductor diodes, transistors

Informative references
Attention is drawn to the following places, which may be of interest for search:
Digital memories
Devices integrating bulk bi-stable switching components, e.g. RRAM cells
Electronic switching circuits
Synonyms and Keywords

In patent documents the following abbreviations are oftern used:

NDR
Negative differential resistance
including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part
Definition statement
This subclass/group covers:

Semiconductor devices wherein the active layer or part of it is made of an organic material (or combination organic and inorganic). This covers organic ICs, organic solar cells, organic imagers, organic displays.

[N: Integrated circuits having a three-dimensional layout]
Definition statement
This subclass/group covers:

Monolithically stacked organic semiconductor devices

References relevant to classification in this group
This subclass/group does not cover:
Monolithically stacked light sensitive devices
Integration of organic light emitting devices
[N: comprising components of the field-effect type]
Definition statement
This subclass/group covers:

Integration of an OTFT with another device falling under the definition of H01L, e.g. inverters:

EP2006929

[N: Integrated circuits with a common active layer, e.g. cross point devices]
Definition statement
This subclass/group covers:

Cross point devices, e.g.:

EP2096672.

References relevant to classification in this group
This subclass/group does not cover:
Resistance random access memory [RRAM] elements comprising cells based on organic memory material
Digital stores using elements whose operation depends on a chemical change
[N: with an active region comprising an inorganic semiconductor]
Definition statement
This subclass/group covers:

Combination of an organic TFT with an inorganic TFT

US 6528816

[N: Combination of organic light sensitive components with organic light emitting components, e.g. optocoupler]
Definition statement
This subclass/group covers:

Example:

WO2008042859

References relevant to classification in this group
This subclass/group does not cover:
Integration of an OLED display with a photo sensor.
Integration of a photodiode in each cell of an OLED display to measure the emission of the OLED and to adjust the intensity accordingly
with components specially adapted for sensing infra-red radiation, light, electromagnetic radiation of shorter wavelength, or corpuscular radiation; with components specially adapted for either the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
Informative references
Attention is drawn to the following places, which may be of interest for search:
Integration of inorganic energy conversion devices
Integration of inorganic devices controlled by radiation, e.g. inorganic CCDs
[N: Energy conversion devices]
Definition statement
This subclass/group covers:

Organic solar cell modules; assembly of organic light sensitive devices specially adapted for conversion of light into electrical energy.

[N: comprising multiple junctions, e.g. tandem cells]
Definition statement
This subclass/group covers:

Organic tandem solar cells

WO02101838

[N: in form of a fibre or a tube, e.g. photovoltaic fibres]
Definition statement
This subclass/group covers:

Fibres based on organic photovoltaic cells.

WO2007130025

[N: Devices controlled by radiation]
Definition statement
This subclass/group covers:

Organic light sensitive devices specially adapted for the measuring of light intensity or light colour.

Informative references
Attention is drawn to the following places, which may be of interest for search:
Investigating or analysing materials by the use of optical means
[N: Imager structures]
Definition statement
This subclass/group covers:

Imager structures based on organic light sensitive devices.

US2007120045

[N: Devices specially adapted for detecting X-ray radiation]
Informative references
Attention is drawn to the following places, which may be of interest for search:
Measuring X-radiation
Devices consisting of a plurality of semiconductor or other solid state components formed in or on a common substrate with components using organic material as the active part specially adapted for light emission, e.g. flat-panel displays using organic light-emitting diodes (OLED)
Definition statement
This subclass/group covers:

Arrangements of OLEDs such as OLED displays or OLED integrated with another component

References relevant to classification in this group
This subclass/group does not cover:
Single OLEDs
Organic semiconducting materials for OLEDs
Single step processes for manufacturing OLED devices
Multistep processes for the manufacture of OLED display
Aspects of electrodes
Aspects of encapsulation
Aspects of light extraction
Aspects of contrast improvement
Assemblies of OLEDs
Circuit arrangements for driving OLED displays
Informative references
Attention is drawn to the following places, which may be of interest for search:
LCD-displays
Plasma displays
Inorganic LED-displays
FE-displays
2D-radiation sources
Surface treatment of glass substrates by at least two coatings
Optical coatings
Chemical coating by decomposition of gaseous compounds
Glossary of terms
In this subclass/group, the following terms (or expressions) are used with the meaning indicated:
OLED display
Organic light emitting diode display
TOLED display
Transparent OLED display
AMOLED display
Active matrix OLED display
PMOLED display
Passive matrix OLED display
OTFT array
Organic thin film transistor array
TFT array
Thin film transistor array
CCM
Colour changing medium
RGB
Red Green Blue
RGBW
Red Green Blue White
[N: OLEDs electrically connected in parallel]
Definition statement
This subclass/group covers:

Arrangements of OLEDs connected in parallel or series and parallel

Examples

US 2004/233140

US 2007/222746

Informative references
Attention is drawn to the following places, which may be of interest for search:
OLED logos
[N: OLEDs electrically connected in series]
Definition statement
This subclass/group covers:

Arrangements of OLEDs connected in series or series and parallel frequently used for illumination or fixed information purposes.

Examples

EP 1 970 960 A2

US2008218061

References relevant to classification in this group
This subclass/group does not cover:
Informative references
Attention is drawn to the following places, which may be of interest for search:
OLED logos
[N: Multi-colour light emission]
Definition statement
This subclass/group covers:

In the headgroup H01L 27/3206, multi-colour OLED displays in which the RGB sub-pixels are formed with an identical emissive layer making use of resonant cavity (adapting the optical path length).

Example:

EP1672962:

The sub-pixels each have an identical em