United States Patent and Trademark Office OG Notices: 15 July 2003

                                    Errata

   "All reference to Patent No. 6,566,237 to Trung T. Doan, et
al of Idaho, for CONTROLLABLE OVONIC PHASE-CHANGE SEMICONDUCTOR MEMORY
DEVICE AND METHODS OF FABRICATING THE SAME appearing in the Official
Gazette of May 20, 2003 shoud be deleted since no patent was
granted."

   "All reference to Patent No. 6,566,531 to Hyung Sik Kim, et
al of Daejeon, Korea, Republic of, for PREPARATION METHOD OF
3-NITRO-1,2,4-TRIAZOL-5-ONE BY A PROCESS MINIMIZING HEAT GENERATION
DURING CRYSTALIZATION appearing in the Official Gazette of May 20, 2003
should be deleted since no patent was granted."

   "All reference to Patent 6,566,825 to James R. Jennings, et
al of Knoxville, TN for HORIZONTAL DRIVE CIRCUIT INCORPORATING AN
INTEGRATED BOOST SWITCH-MODE POWER SUPPLY FOR A CRT DISPLAY appearing
in the Official Gazette of May 20, 2003 should be deleted since no
patent was granted."

   "All reference to Patent No. 6,567,089 to Ken Chen, et al of
Saratoga, CA for THREE DIMENSIONAL GRAPHIC PROCESSOR appearing in the
Official Gazette of May 20, 2003 should be deleted since no patent was
granted."

   "All reference to Patent No. 6,567,090 to Satoshi Hirotsume,
et al of Japan, for IMAGE PROCESSOR AND IMAGE DISPLAY appearing in the
Official Gazette of May 20, 2003 should be deleted since no patent was
granted."

   "All reference to Patent No. 6,567,245 to Kazuhiko Hayashi of
Japan, for MAGNETO-RESISTANCE EFFECT HEAD AND MAGNETIC STORAGE DEVICE
EMPLOYING THE HEAD appearing in the Official Gazette of May 20, 2003
should be deleted since no patent was granted."

   "All reference to Patent No. 6,567,872 to Toshiharu
Kobayashi, et al of Tokyo, Japan for EXTERNAL STORAGE WHICH CAN BE
CONNECTED TO A PLURALITY OF ELECTRONIC DEVICES HAVING DIFFERENT TYPES
OF BUILT-IN INTERFACE WITHOUT USING A CONVERSION ADAPTER appearing in
the Official Gazette of May 20, 2003 should be deleted since no patent
was granted."

   "All reference to Patent No. 6,567,945 to Hideyuki Nakamura
of Tokyo, Japan for MEMORY-MOUNTING INTEGRATED CIRCUIT AND TEST METHOD
THEREOF appearing in the Official Gazette of May 20, 2003 should be
deleted since no patent was granted."