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ELECTRONIC DIGITAL LOGIC CIRCUITRY
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| 1 | ![[Patents]](../gifs/ps.gif) | SUPERCONDUCTOR (E.G., CRYOGENIC, ETC.) |
| 2 | ![[Patents]](../gifs/ps.gif) | . Tunneling device |
| 3 | ![[Patents]](../gifs/ps.gif) | . . Josephson tunneling device |
| 4 | ![[Patents]](../gifs/ps.gif) | . . . Plural devices (e.g., distributive device, etc.) |
| 5 | ![[Patents]](../gifs/ps.gif) | . . . Interference device (i.e., SQUID) |
| 6 | ![[Patents]](../gifs/ps.gif) | . . Function of AND, OR, NAND, NOR, or NOT |
| 7 | ![[Patents]](../gifs/ps.gif) | . Function of AND, OR, NAND, NOR, or NOT |
| 8 | ![[Patents]](../gifs/ps.gif) | SECURITY (E.G., ACCESS OR COPY PREVENTION, ETC.) |
| 9 | ![[Patents]](../gifs/ps.gif) | RELIABILITY |
| 10 | ![[Patents]](../gifs/ps.gif) | . Redundant |
| 11 | ![[Patents]](../gifs/ps.gif) | . . Voter circuit (e.g., majority logic, etc.) |
| 12 | ![[Patents]](../gifs/ps.gif) | . . With flip-flop |
| 13 | ![[Patents]](../gifs/ps.gif) | . . With field effect-transistor |
| 14 | ![[Patents]](../gifs/ps.gif) | . Fail-safe |
| 15 | ![[Patents]](../gifs/ps.gif) | . Parasitic prevention in integrated circuit structure |
| 16 | ![[Patents]](../gifs/ps.gif) | WITH TEST FACILITATING FEATURE |
| 17 | ![[Patents]](../gifs/ps.gif) | ACCELERATING SWITCHING |
| 18 | ![[Patents]](../gifs/ps.gif) | . Bipolar transistor |
| 19 | ![[Patents]](../gifs/ps.gif) | . . With Schottky device |
| 20 | ![[Patents]](../gifs/ps.gif) | . . . Complementary transistors |
| 21 | ![[Patents]](../gifs/ps.gif) | SIGNAL SENSITIVITY OR TRANSMISSION INTEGRITY |
| 22 | ![[Patents]](../gifs/ps.gif) | . Input noise margin enhancement |
| 23 | ![[Patents]](../gifs/ps.gif) | . . With field effect-transistor |
| 24 | ![[Patents]](../gifs/ps.gif) | . . . Complementary FET`s |
| 25 | ![[Patents]](../gifs/ps.gif) | . . . Depletion or enhancement |
| 26 | ![[Patents]](../gifs/ps.gif) | . Output switching noise reduction |
| 27 | ![[Patents]](../gifs/ps.gif) | . . With field effect-transistor |
| 28 | ![[Patents]](../gifs/ps.gif) | . . . With clocking |
| 29 | ![[Patents]](../gifs/ps.gif) | . Pulse shaping (e.g., squaring, etc.) |
| 30 | ![[Patents]](../gifs/ps.gif) | . Bus or line termination (e.g., clamping, impedance matching, etc.) |
| 31 | ![[Patents]](../gifs/ps.gif) | . Signal level or switching threshold stabilization |
| 32 | ![[Patents]](../gifs/ps.gif) | . . Temperature compensation |
| 33 | ![[Patents]](../gifs/ps.gif) | . . Bias or power supply level stabilization |
| 34 | ![[Patents]](../gifs/ps.gif) | . . With field effect-transistor |
| 35 | ![[Patents]](../gifs/ps.gif) | THRESHOLD (E.G., MAJORITY, MINORITY, OR WEIGHTED INPUTS, ETC.) |
| 36 | ![[Patents]](../gifs/ps.gif) | . With field effect-transistor |
| 37 | ![[Patents]](../gifs/ps.gif) | MULTIFUNCTIONAL OR PROGRAMMABLE (E.G., UNIVERSAL, ETC.) |
| 38 | ![[Patents]](../gifs/ps.gif) | . Having details of setting or programming of interconnections or logic functions |
| 39 | ![[Patents]](../gifs/ps.gif) | . Array (e.g., PLA, PAL, PLD, etc.) |
| 40 | ![[Patents]](../gifs/ps.gif) | . . With flip-flop or sequential device |
| 41 | ![[Patents]](../gifs/ps.gif) | . . Significant integrated structure, layout, or layout interconnections |
| 42 | ![[Patents]](../gifs/ps.gif) | . . Bipolar transistor |
| 43 | ![[Patents]](../gifs/ps.gif) | . . . Emitter-coupled logic or emitter-follower logic |
| 44 | ![[Patents]](../gifs/ps.gif) | . . Field effect transistor |
| 45 | ![[Patents]](../gifs/ps.gif) | . . . Complementary FET`s |
| 46 | ![[Patents]](../gifs/ps.gif) | . Sequential (i.e., finite state machine) or with flip-flop |
| 47 | ![[Patents]](../gifs/ps.gif) | . Significant integrated structure, layout, or layout interconnections |
| 48 | ![[Patents]](../gifs/ps.gif) | . Bipolar transistor |
| 49 | ![[Patents]](../gifs/ps.gif) | . Field-effect transistor |
| 50 | ![[Patents]](../gifs/ps.gif) | . . Complementary FET`s |
| 51 | ![[Patents]](../gifs/ps.gif) | INHIBITOR |
| 52 | ![[Patents]](../gifs/ps.gif) | EXCLUSIVE FUNCTION (E.G., EXCLUSIVE OR, ETC.) |
| 53 | ![[Patents]](../gifs/ps.gif) | . Half-adder or quarter-adder |
| 54 | ![[Patents]](../gifs/ps.gif) | . Exclusive NOR |
| 55 | ![[Patents]](../gifs/ps.gif) | . With field-effect transistor |
| 56 | ![[Patents]](../gifs/ps.gif) | TRI-STATE (I.E., HIGH IMPEDANCE AS THIRD STATE) |
| 57 | ![[Patents]](../gifs/ps.gif) | . With field effect-transistor |
| 58 | ![[Patents]](../gifs/ps.gif) | . . Complementary FET`s |
| 59 | ![[Patents]](../gifs/ps.gif) | THREE OR MORE ACTIVE LEVELS (E.G., TERNARY, QUATENARY, ETC.) |
| 60 | ![[Patents]](../gifs/ps.gif) | . With conversion (e.g., three level to two level, etc.) |
| 61 | ![[Patents]](../gifs/ps.gif) | INSULATED GATE CHARGE TRANSFER DEVICE |
| 62 | ![[Patents]](../gifs/ps.gif) | INTERFACE (E.G., CURRENT DRIVE, LEVEL SHIFT, ETC.) |
| 63 | ![[Patents]](../gifs/ps.gif) | . Logic level shifting (i.e., interface between devices of different logic families) |
| 64 | ![[Patents]](../gifs/ps.gif) | . . Bi-CMOS |
| 65 | ![[Patents]](../gifs/ps.gif) | . . . TTL to/from CMOS |
| 66 | ![[Patents]](../gifs/ps.gif) | . . . ECL to/from CMOS |
| 67 | ![[Patents]](../gifs/ps.gif) | . . . ECL to/from TTL |
| 68 | ![[Patents]](../gifs/ps.gif) | . . Field-effect transistor (e.g., JFET, MOSFET, etc.) |
| 69 | ![[Patents]](../gifs/ps.gif) | . . . ECL to/from GaAs FET (e.g., MESFET, etc.) |
| 70 | ![[Patents]](../gifs/ps.gif) | . . . TTL to/from MOS |
| 71 | ![[Patents]](../gifs/ps.gif) | . . . . TTL to/from CMOS |
| 72 | ![[Patents]](../gifs/ps.gif) | . . . . . Using depletion or enhancement transistors |
| 73 | ![[Patents]](../gifs/ps.gif) | . . . ECL to/from MOS |
| 74 | ![[Patents]](../gifs/ps.gif) | . . . ECL to/from TTL |
| 75 | ![[Patents]](../gifs/ps.gif) | . . Bipolar transistor |
| 76 | ![[Patents]](../gifs/ps.gif) | . . . TTL to/from MOS |
| 77 | ![[Patents]](../gifs/ps.gif) | . . . ECL to/from MOS |
| 78 | ![[Patents]](../gifs/ps.gif) | . . . ECL to/from TTL |
| 79 | ![[Patents]](../gifs/ps.gif) | . . . Integrated Injection Logic (I2L) |
| 80 | ![[Patents]](../gifs/ps.gif) | . Supply voltage level shifting (i.e., interface between devices of a same logic family with different operating voltage levels) |
| 81 | ![[Patents]](../gifs/ps.gif) | . . CMOS |
| 82 | ![[Patents]](../gifs/ps.gif) | . Current driving (e.g., fan in/out, off chip driving, etc.) |
| 83 | ![[Patents]](../gifs/ps.gif) | . . Field-effect transistor |
| 84 | ![[Patents]](../gifs/ps.gif) | . . . Bi-CMOS |
| 85 | ![[Patents]](../gifs/ps.gif) | . . . . Having plural output pull-up or pull-down transistors |
| 86 | ![[Patents]](../gifs/ps.gif) | . . . Bus driving |
| 87 | ![[Patents]](../gifs/ps.gif) | . . . Having plural output pull-up or pull-down transistors |
| 88 | ![[Patents]](../gifs/ps.gif) | . . . With capacitive or inductive bootstrapping |
| 89 | ![[Patents]](../gifs/ps.gif) | . . Bipolar transistor |
| 90 | ![[Patents]](../gifs/ps.gif) | . . . Bus driving |
| 91 | ![[Patents]](../gifs/ps.gif) | . . . Having plural output pull-up or pull-down transistors |
| 92 | ![[Patents]](../gifs/ps.gif) | . . . With capacitive or inductive bootstrapping |
| 93 | ![[Patents]](../gifs/ps.gif) | CLOCKING OR SYNCHRONIZING OF LOGIC STAGES OR GATES |
| 94 | ![[Patents]](../gifs/ps.gif) | . Metastable state prevention |
| 95 | ![[Patents]](../gifs/ps.gif) | . Field-effect transistor |
| 96 | ![[Patents]](../gifs/ps.gif) | . . Two or more clocks (e.g., phase clocking, etc.) |
| 97 | ![[Patents]](../gifs/ps.gif) | . . . MOSFET |
| 98 | ![[Patents]](../gifs/ps.gif) | . . MOSFET |
| 99 | ![[Patents]](../gifs/ps.gif) | HAVING LOGIC LEVELS CONVEYED BY SIGNAL FREQUENCY OR PHASE |
| 100 | ![[Patents]](../gifs/ps.gif) | INTEGRATED INJECTION LOGIC |
| 101 | ![[Patents]](../gifs/ps.gif) | SIGNIFICANT INTEGRATED STRUCTURE, LAYOUT, OR LAYOUT INTERCONNECTIONS |
| 102 | ![[Patents]](../gifs/ps.gif) | . Field-effect transistor |
| 103 | ![[Patents]](../gifs/ps.gif) | . . Complementary FET`s |
| 104 | ![[Patents]](../gifs/ps.gif) | FUNCTION OF AND, OR, NAND, NOR, or NOT |
| 105 | ![[Patents]](../gifs/ps.gif) | . Decoding |
| 106 | ![[Patents]](../gifs/ps.gif) | . . With field-effect transistor |
| 107 | ![[Patents]](../gifs/ps.gif) | . . . Depletion or enhancement |
| 108 | ![[Patents]](../gifs/ps.gif) | . . . CMOS |
| 109 | ![[Patents]](../gifs/ps.gif) | . Bipolar and FET |
| 110 | ![[Patents]](../gifs/ps.gif) | . . Bi-CMOS |
| 111 | ![[Patents]](../gifs/ps.gif) | . Space discharge device (e.g., vacuum tube, etc.) |
| 112 | ![[Patents]](../gifs/ps.gif) | . Field-effect transistor (e.g., JFET, etc.) |
| 113 | ![[Patents]](../gifs/ps.gif) | . . Pass transistor logic or transmission gate logic |
| 114 | ![[Patents]](../gifs/ps.gif) | . . Wired logic (e.g., wired-OR, wired-AND, dotted logic, etc.) |
| 115 | ![[Patents]](../gifs/ps.gif) | . . Source-coupled logic (e.g., current mode logic (CML), differential current switch logic (DCSL), etc.) |
| 116 | ![[Patents]](../gifs/ps.gif) | . . Schottky-gate FET (i.e., MESFET) |
| 117 | ![[Patents]](../gifs/ps.gif) | . . . Depletion or enhancement |
| 118 | ![[Patents]](../gifs/ps.gif) | . . . Diode transistor logic |
| 119 | ![[Patents]](../gifs/ps.gif) | . . MOSFET (i.e., metal-oxide semiconductor field-effect transistor) |
| 120 | ![[Patents]](../gifs/ps.gif) | . . . Depletion or enhancement |
| 121 | ![[Patents]](../gifs/ps.gif) | . . . CMOS |
| 122 | ![[Patents]](../gifs/ps.gif) | . . Complementary FET`s |
| 123 | ![[Patents]](../gifs/ps.gif) | . . With semiconductor diode or negative resistance device |
| 124 | ![[Patents]](../gifs/ps.gif) | . Bipolar transistor (e.g., RTL, DCTL, etc.) |
| 125 | ![[Patents]](../gifs/ps.gif) | . . Wired logic or open collector logic (e.g., wired-OR, wired-AND, dotted logic, etc.) |
| 126 | ![[Patents]](../gifs/ps.gif) | . . Emitter-coupled or emitter-follower logic |
| 127 | ![[Patents]](../gifs/ps.gif) | . . . Current mode logic (CML) |
| 128 | ![[Patents]](../gifs/ps.gif) | . . Transistor-transistor logic (TTL) |
| 129 | ![[Patents]](../gifs/ps.gif) | . . . Complementary transistor logic (CTL) |
| 130 | ![[Patents]](../gifs/ps.gif) | . . Diode-transistor logic (DTL) |
| 131 | ![[Patents]](../gifs/ps.gif) | . . . With metal semiconductor junction diode (e.g., Schottky barrier, etc.) |
| 132 | ![[Patents]](../gifs/ps.gif) | . . With negative resistance device (e.g., tunnel diode, thyristor, etc.) |
| 133 | ![[Patents]](../gifs/ps.gif) | . Diode |
| 134 | ![[Patents]](../gifs/ps.gif) | . . Negative resistance diode (e.g., tunnel, gunn, etc.) |
| 135 | ![[Patents]](../gifs/ps.gif) | . Negative resistance device |
| 136 | ![[Patents]](../gifs/ps.gif) | MISCELLANEOUS |