File Diff Report

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Reference is made to <figref idref="DRAWINGS">FIG. 3</figref>, which is a circuit diagram of the electric energy converter of the present invention. The electric energy converter 3 assembly composes of an IC U5, some resistors, some capacitors and some LEDs, wherein the type of the IC U5 is SC806. The IC U5 of type SC806 includes the IN pin, the VCC pin, the STAT1 pin, the STAT2 pin, the VSS pin, the OUT pin, the BAT pin, the TS pin, the {overscore (PG)} pin and the ISET pin.

The IN pin of the IC U5 connects to the storage device 4 via a capacitor C24, the VCC pin connects to a LED D3 via a resistor R21, the STAT1 pin connects to the solar energy panel 2 via a resistor R31 and a capacitor C25. Moreover, the STAT2 pin and the VSS pin connect to a resistor R30 and a resistor R29 respectively, the OUT pin connects to a LED D2 via a resistor R18, the BAT pin connects to a resistor R28. Furthermore, the TS pin is floating and the {overscore (PG)} pin and the ISET pin connect to a ground terminal.

The IN pin of the IC U5 connects to the storage device 4 via a capacitor C24, the VCC pin connects to a LED D3 via a resistor R21, the STAT1 pin connects to the solar energy panel 2 via a resistor R31 and a capacitor C25. Moreover, the STAT2 pin and the VSS pin connect to a resistor R30 and a resistor R29 respectively, the OUT pin connects to a LED D2 via a resistor R18, the BAT pin connects to a resistor R28. Furthermore, the TS pin is floating and the <o ostyle="single">PG</o> pin and the ISET pin connect to a ground terminal.

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<sequence-list file="US20070007148A1-20070111-SEQLST.XML" carriers="internal-electronic" seq-file-type="ST.25"/>

<sequence-list file="US20070007148A1-20070111-S00001.XML" carriers="internal-electronic" seq-file-type="ST.25"/>

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The relevant figures of merit to judge the feasibility to bring such an atomic cluster to a hover are the number of atoms in the trap and its size, the intensity and wavelength of the laser light, and the average intermolecular distance. Consider N=102 atoms in a trap with D≈2×10−7 cm, which yields an intermolecular distance {overscore (R)}˜D/N1/3≈10a0. Now let us have 18 (six triads [22]) high-power lasers each outputting 2.5 kW into a 0.5 cm diameter beam at a wavelength λL≈1000 Å. Appropriately focused onto the trap size, this would yield an intensity I≈1.3×1017 W/cm2. By moderate off-resonance detuning, it is possible to obtain dramatic increases in atomic polarizability over its static value [23] (another approach may consist of using a cold gas of highly excited Rydberg atoms, since, in this case, the polarizability is proportional to n7, where n is the principal quantum number). By adopting αA(kL)≈3×105α0, and by substituting the above numerical values into Eq. (14) in c. g. s. units, we find alift,zgas/g≈+1.5, that is, the system will hover unsupported in the gravitational field of the earth or accelerate upward.

The relevant figures of merit to judge the feasibility to bring such an atomic cluster to a hover are the number of atoms in the trap and its size, the intensity and wavelength of the laser light, and the average intermolecular distance. Consider N=102 atoms in a trap with D≈2×10−7 cm, which yields an intermolecular distance <o ostyle="single">R</o>˜D/N1/3≈10a0. Now let us have 18 (six triads [22]) high-power lasers each outputting 2.5 kW into a 0.5 cm diameter beam at a wavelength λL≈1000 Å. Appropriately focused onto the trap size, this would yield an intensity I≈1.3×1017 W/cm2. By moderate off-resonance detuning, it is possible to obtain dramatic increases in atomic polarizability over its static value [23] (another approach may consist of using a cold gas of highly excited Rydberg atoms, since, in this case, the polarizability is proportional to n7, where n is the principal quantum number). By adopting αA(kL)≈3×105α0, and by substituting the above numerical values into Eq. (14) in c. g. s. units, we find alift,zgas/g≈+1.5, that is, the system will hover unsupported in the gravitational field of the earth or accelerate upward.

Let us consider a gas of NA identical atoms of mass mA, polarizability αA2(kL), confined within an appropriate trap of such dimensions as to correspond to an average interatomic distance {overscore (R)}. In what follows, we shall assume that the number of atoms, NA, the size of the trap, D, and the average interatomic distance, {overscore (R)}, are related simply as D˜{overscore (R)}NA1/3. In addition, Thirunamachandran's theory of dispersion forces under the effect of illumination also requires the constraint that λL>>{overscore (R)}[21].

Let us consider a gas of NA identical atoms of mass mA, polarizability αA2(kL), confined within an appropriate trap of such dimensions as to correspond to an average interatomic distance <o ostyle="single">R</o>. In what follows, we shall assume that the number of atoms, NA, the size of the trap, D, and the average interatomic distance, <o ostyle="single">R</o>, are related simply as D˜ <o ostyle="single">R</o>NA1/3. In addition, Thirunamachandran's theory of dispersion forces under the effect of illumination also requires the constraint that λL>> <o ostyle="single">R</o>[21].

where the relationship between total power and intensity at Eq. (48) was used. Let us consider only the s-state polarizability as αn(λL)=αnr(2an)3 and let us write the average intermolecular distance in terms of the atomic radius as {overscore (R)}={overscore (r)}an. Finally, by recalling that an=a0n2, we find:

where the relationship between total power and intensity at Eq. (48) was used. Let us consider only the s-state polarizability as αn(λL)=αnr(2an)3 and let us write the average intermolecular distance in terms of the atomic radius as <o ostyle="single">R</o>= <o ostyle="single">r</o>an. Finally, by recalling that an=a0n2, we find:

At this rate, the average final velocity of the atoms will be vA, fin=√{square root over (2aA(D/2))}:

At this rate, the average final velocity of the atoms will be vA, fin=√{square root over (2aA(D/2))}:

<?in-line-formulae description="In-line Formulae" end="lead"?>W=18 I NA2/3{overscore (R)}2. (48) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>W=18 I NA2/3 <o ostyle="single">R</o>2. (48) <?in-line-formulae description="In-line Formulae" end="tail"?>

independently of g. For practical reasons, let us rewrite this result in units of Megawatts (MW) in terms of the wavelength in micrometers, λ(μm), of the average interatomic distance in units of Bohr radii, {overscore (R)}/a0, and by involving the dimensionless polarizability factor as αA(kL)=αnr(kL)α0:

independently of g. For practical reasons, let us rewrite this result in units of Megawatts (MW) in terms of the wavelength in micrometers, λ(μm), of the average interatomic distance in units of Bohr radii, <o ostyle="single">R</o>/a0, and by involving the dimensionless polarizability factor as αA(kL)=αnr(kL)α0:

<entry>{overscore (R)} = 5 a0</entry>

<claim-text>{overscore (R)}/a0: is the average interatomic distance, in Bohr radii; </claim-text>

<claim-text> <o ostyle="single">R</o>/a0: is the average interatomic distance, in Bohr radii; </claim-text>

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The controller 20 then calculates 34 the X and Y Cartesian coordinate centroid XC and YC of the impinging laser beam 12. The laser centroid calculation algorithm 34 also receives each individual detected pixel M magnitude that preferably exceeds the predetermined threshold value. The centroid is computed using two {overscore (X)} and {overscore (Y)} centroid equations for computing {overscore (X)} and {overscore (Y)} centroids.

The controller 20 then calculates 34 the X and Y Cartesian coordinate centroid XC and YC of the impinging laser beam 12. The laser centroid calculation algorithm 34 also receives each individual detected pixel M magnitude that preferably exceeds the predetermined threshold value. The centroid is computed using two <o ostyle="single">X</o> and <o ostyle="single">Y</o> centroid equations for computing <o ostyle="single">X</o> and <o ostyle="single">Y</o> centroids.

In the {overscore (X)} and {overscore (Y)} centroid equations, Pix_Val is the respective magnitude M of detected pixels, the subscripts i and j represent the individual column i-th number and j-th row number for the pixel being inputted into the respective centroiding equations. The {overscore (X)} and {overscore (Y)} centroid calculations are made, and updated on a real-time basis. That is, every time a detected pixel is received, new values of the {overscore (X)} and {overscore (Y)} centroid are calculated. The {overscore (X)} and {overscore (Y)} centroid calculation algorithm 34 operates on a real-time basis in that only those pixels which were passed to it from the laser detection algorithm 32 are processed. When a current pixel is not detected as a detected pixel, then the centroid calculation algorithm 34 remains idle and maintains the last calculated values waiting for data for the next detected pixel. Further updated values are calculated only when detected pixel data is inputted. When an impinging laser beam only illuminates an extreme edge of the focal plane array 14, such as in the most upper or lowest row, or the extreme left or right column of the array is illuminated, no adverse effect occurs in the centroid computation. The centroid algorithm 34 performs the centroid calculations without edge effects.

In the <o ostyle="single">X</o> and <o ostyle="single">Y</o> centroid equations, Pix_Val is the respective magnitude M of detected pixels, the subscripts i and j represent the individual column i-th number and j-th row number for the pixel being inputted into the respective centroiding equations. The <o ostyle="single">X</o> and <o ostyle="single">Y</o> centroid calculations are made, and updated on a real-time basis. That is, every time a detected pixel is received, new values of the <o ostyle="single">X</o> and <o ostyle="single">Y</o> centroid are calculated. The <o ostyle="single">X</o> and <o ostyle="single">Y</o> centroid calculation algorithm 34 operates on a real-time basis in that only those pixels which were passed to it from the laser detection algorithm 32 are processed. When a current pixel is not detected as a detected pixel, then the centroid calculation algorithm 34 remains idle and maintains the last calculated values waiting for data for the next detected pixel. Further updated values are calculated only when detected pixel data is inputted. When an impinging laser beam only illuminates an extreme edge of the focal plane array 14, such as in the most upper or lowest row, or the extreme left or right column of the array is illuminated, no adverse effect occurs in the centroid computation. The centroid algorithm 34 performs the centroid calculations without edge effects.

The pointing positioner 22 is continuously controlled, in real-time and in a closed-loop. The WOI is preferably centered about the centroid XC and YC. The size of the WOI can be increased to include a variably sized window margin. The window margin of a predetermined size reduces jitter of the illuminated pixel as well as reducing jitter in pointing the sensor 14 by the positioner 22. The pointing algorithm 36 controls the output timing of the pointing commands sent to the sensor pointing positioner 22. The pointing algorithm 34 always holds the most current calculated value of {overscore (X)} and {overscore (Y)} centroids computed by the centroid calculation algorithms. The {overscore (X)} and {overscore (Y)} centroid outputs define a center pixel XC and YC that are X and Y Cartesian coordinates centroid values of the impinging laser spot upon the focal plane array 14.

The pointing positioner 22 is continuously controlled, in real-time and in a closed-loop. The WOI is preferably centered about the centroid XC and YC. The size of the WOI can be increased to include a variably sized window margin. The window margin of a predetermined size reduces jitter of the illuminated pixel as well as reducing jitter in pointing the sensor 14 by the positioner 22. The pointing algorithm 36 controls the output timing of the pointing commands sent to the sensor pointing positioner 22. The pointing algorithm 34 always holds the most current calculated value of <o ostyle="single">X</o> and <o ostyle="single">Y</o> centroids computed by the centroid calculation algorithms. The <o ostyle="single">X</o> and <o ostyle="single">Y</o> centroid outputs define a center pixel XC and YC that are X and Y Cartesian coordinates centroid values of the impinging laser spot upon the focal plane array 14.

The pointing command from the pointing algorithm 36 allows the positioner 22 to maintain continuous, high-speed and precise microradian and picoradian pointing resolutions for tracking of the impinging laser beam 12 maintained within array 16. The {overscore (X)} and {overscore (Y)} centroid outputs of each centroiding calculation are effectively pointing commands. The pointing command provides coordinate direction and a number of pixels by rows and columns. The pointing positioner 22 is commanded to rotate the focal plane array 16 for the focal plane array 16 to be able to continuously and precisely track the laser beam 12. The {overscore (X)} and {overscore (Y)} values are digital pointing commands. The pointing algorithm 36 may be modified so that the output {overscore (X)} and {overscore (Y)} centroid outputs may be based upon either a per frame basis, or averaged over a preassigned number of frames. Further, the controller 20 could be modified to receive requests from the positioner 22 to controller for an updated centroid pointing command. The system could be modified so that the FPGA controller 20 receives requests from the positioner 22 when the positioner sends a request signal to the FPGA controller 20 requesting updated pointing commands. In this manner, the pointing algorithm 36 is adaptable to existing pointing positioners providing requests for pointing commands. The pointing command and window sizing commands are adjusted to keep the incoming laser beam 12 near the center of the focal plane array 16 so as to position the illumination spot within the WOI and about the center of the FPA 16.

The pointing command from the pointing algorithm 36 allows the positioner 22 to maintain continuous, high-speed and precise microradian and picoradian pointing resolutions for tracking of the impinging laser beam 12 maintained within array 16. The <o ostyle="single">X</o> and <o ostyle="single">Y</o> centroid outputs of each centroiding calculation are effectively pointing commands. The pointing command provides coordinate direction and a number of pixels by rows and columns. The pointing positioner 22 is commanded to rotate the focal plane array 16 for the focal plane array 16 to be able to continuously and precisely track the laser beam 12. The <o ostyle="single">X</o> and <o ostyle="single">Y</o> values are digital pointing commands. The pointing algorithm 36 may be modified so that the output <o ostyle="single">X</o> and <o ostyle="single">Y</o> centroid outputs may be based upon either a per frame basis, or averaged over a preassigned number of frames. Further, the controller 20 could be modified to receive requests from the positioner 22 to controller for an updated centroid pointing command. The system could be modified so that the FPGA controller 20 receives requests from the positioner 22 when the positioner sends a request signal to the FPGA controller 20 requesting updated pointing commands. In this manner, the pointing algorithm 36 is adaptable to existing pointing positioners providing requests for pointing commands. The pointing command and window sizing commands are adjusted to keep the incoming laser beam 12 near the center of the focal plane array 16 so as to position the illumination spot within the WOI and about the center of the FPA 16.

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<figref idref="DRAWINGS">FIG. 2</figref>a firstly shows in a three-dimensional view how intrinsic birefringence in the calcium fluoride material is related to the crystal directions if the lens axis EA faces in the <100>-crystal direction. The Figure shows a round plane-parallel plate 201 of calcium fluoride. In this case the lens axis EA points in the <100>-crystal direction. Besides the <100>-crystal direction the <101>-, <1 {overscore (1)}0>-, <10 {overscore (1)}>- and <110>-crystal directions are also shown as arrows. Intrinsic birefringence is diagrammatically illustrated by four “lobes” 203, the surface areas of which specify the magnitude of intrinsic birefringence for the respective beam direction of a light beam. Maximum intrinsic birefringence occurs in the <101>-, <1 {overscore (1)}0>-, <10 {overscore (1)}>- and <110>-crystal directions, that is to say for light beams with a spread angle of 45° and an azimuth angle of 0°, 90°, 180° and 270° within the lens. For azimuth angles of 45°, 135°, 225° and 315° there are minimum values in respect of intrinsic birefringence. Intrinsic birefringence disappears for a spread angle of 0°.

<figref idref="DRAWINGS">FIG. 2</figref>a firstly shows in a three-dimensional view how intrinsic birefringence in the calcium fluoride material is related to the crystal directions if the lens axis EA faces in the <100>-crystal direction. The Figure shows a round plane-parallel plate 201 of calcium fluoride. In this case the lens axis EA points in the <100>-crystal direction. Besides the <100>-crystal direction the <101>-, <1 <o ostyle="single">1</o>0>-, <10 <o ostyle="single">1</o>>- and <110>-crystal directions are also shown as arrows. Intrinsic birefringence is diagrammatically illustrated by four “lobes” 203, the surface areas of which specify the magnitude of intrinsic birefringence for the respective beam direction of a light beam. Maximum intrinsic birefringence occurs in the <101>-, <1 <o ostyle="single">1</o>0>-, <10 <o ostyle="single">1</o>>- and <110>-crystal directions, that is to say for light beams with a spread angle of 45° and an azimuth angle of 0°, 90°, 180° and 270° within the lens. For azimuth angles of 45°, 135°, 225° and 315° there are minimum values in respect of intrinsic birefringence. Intrinsic birefringence disappears for a spread angle of 0°.

<figref idref="DRAWINGS">FIG. 2</figref>c shows in a three-dimensional view how intrinsic birefringence is related to the crystal directions if the lens axis EA faces in the <110>-crystal direction. The Figure shows a round plane-parallel plate 209 of calcium fluoride. In this case the lens axis EA points in the <110>-crystal direction. Besides the <110>-crystal direction the <01 {overscore (1)}>-, <10 {overscore (1)}>-, the <101>- and the <011>-crystal directions are also shown as arrows. Intrinsic birefringence is diagrammatically illustrated by five “lobes” 211 whose surface areas specify the magnitude of intrinsic birefringence for the respective beam direction of a light beam. Maximum intrinsic birefringence occurs on the one hand in the direction of the lens axis EA, and on the other hand respectively in the <01 {overscore (1)}>-, <10 {overscore (1)}>-, <101>- and <011>-crystal directions, that is to say for light beams with a spread angle of 0° or with a spread angle of 60° respectively and the four azimuth angles which are produced by projection of the <01 {overscore (1)}>-, <10 {overscore (1)}>-, <101>- and <011>-crystal directions in the {110}-crystal plane. Such high spread angles however do not occur in crystal material as the maximum spread angles are limited to less than 45° by the refractive index of the crystal.

<figref idref="DRAWINGS">FIG. 2</figref>c shows in a three-dimensional view how intrinsic birefringence is related to the crystal directions if the lens axis EA faces in the <110>-crystal direction. The Figure shows a round plane-parallel plate 209 of calcium fluoride. In this case the lens axis EA points in the <110>-crystal direction. Besides the <110>-crystal direction the <01 <o ostyle="single">1</o>>-, <10 <o ostyle="single">1</o>>-, the <101>- and the <011>-crystal directions are also shown as arrows. Intrinsic birefringence is diagrammatically illustrated by five “lobes” 211 whose surface areas specify the magnitude of intrinsic birefringence for the respective beam direction of a light beam. Maximum intrinsic birefringence occurs on the one hand in the direction of the lens axis EA, and on the other hand respectively in the <01 <o ostyle="single">1</o>>-, <10 <o ostyle="single">1</o>>-, <101>- and <011>-crystal directions, that is to say for light beams with a spread angle of 0° or with a spread angle of 60° respectively and the four azimuth angles which are produced by projection of the <01 <o ostyle="single">1</o>>-, <10 <o ostyle="single">1</o>>-, <101>- and <011>-crystal directions in the {110}-crystal plane. Such high spread angles however do not occur in crystal material as the maximum spread angles are limited to less than 45° by the refractive index of the crystal.

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NMR analysis. 1H-NMR spectrum in CD2Cl2 (200 MHz) shows the following diagnostic peaks: δ 1.1 (18H, t, J=7.4 Hz, ethyl CH3—CH2—); 2.77 (12H, q,ethyl CH3—CH2); 6.46 (1H d, J=2.2 Hz, xanthene-H), 6.5 (1H d, J=2.0 Hz, xanthene-H), 6.57 (2H d, J=2.2 Hz, xanthene-H), 6.85 (1H s, xanthene-H), 6.89 (1H s, xanthene-H); 7.17 (1H m, Jorto=5.5 Hz, Jmeta=3.0 Hz, benzene-H), 7.58 (2H m, Jorto=5.7 Hz, Jmeta=2.9 Hz, benzene-H); 8.07 (1H m, Jorto=5.8 Hz, Jmeta=2.8 Hz, benzene-H).

NMR analysis. 1H-NMR spectrum in CD2Cl2 (200 MHz) shows the following diagnostic peaks: δ 1.1 (18H, t, J=7.4 Hz, ethyl CH3—CH2—); 2.77 (12H, q,ethyl CH3—CH2); 6.46 (1H d, J=2.2 Hz, xanthene-H), 6.5 (1H d, J=2.0 Hz, xanthene-H), 6.57 (2H d, J=2.2 Hz, xanthene-H), 6.85 (1H s, xanthene-H), 6.89 (1H s, xanthene-H); 7.17 (1H m, Jorto=5.5 Hz, Jmeta=3.0 Hz, benzene-H), 7.58 (2H m, Jorto=5.7 Hz, Jmeta=2.9 Hz, benzene-H); 8.07 (1H m, Jorto=5.8 Hz, Jmeta=2.8 Hz, benzene-H).

NMR analysis. 1H-NMR spectrum in CD2Cl2 (200 MHz) exhibits the following diagnostic peaks: δ 1.22 (18H, t, J=7.2 Hz, ethyl CH3—CH2—); 2.94 (12H, q,ethyl CH3—CH2); 7.28 (2H s, xanthene-H); 7.14 (1H m, Jorto=6.0 Hz, benzene-H), 7.55 (2H m, benzene-H); 8.14 (1H m, Jorto=6.9 Hz, benzene-H).

NMR analysis. 1H-NMR spectrum in CD2Cl2 (200 MHz) exhibits the following diagnostic peaks: δ 1.22 (18H, t, J=7.2 Hz, ethyl CH3—CH2—); 2.94 (12H, q,ethyl CH3—CH2); 7.28 (2H s, xanthene-H); 7.14 (1H m, Jorto=6.0 Hz, benzene-H), 7.55 (2H m, benzene-H); 8.14 (1H m, Jorto=6.9 Hz, benzene-H).

NMR analysis. 1H-NMR spectrum in CD2Cl2 (200 MHz) exhibits the following diagnostic peaks: δ 1.22 (18H, t, J=7.2 Hz, ethyl CH3—CH2—); 2.96 (12H, q, ethyl CH3—CH2); 7.52 (2H s, xanthene-H).

NMR analysis. 1H-NMR spectrum in CD2Cl2 (200 MHz) exhibits the following diagnostic peaks: δ 1.22 (18H, t, J=7.2 Hz, ethyl CH3—CH2—); 2.96 (12H, q, ethyl CH3—CH2); 7.52 (2H s, xanthene-H).

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<figref idref="DRAWINGS">FIG. 52</figref> shows a third alternate embodiment of the invention that tends to provide continuous tuning of the filter over temperature, and tends to more accurately keeps the response curve of the filter centered on the desired frequency. This embodiment of the invention preserves the separation of I 5202 and Q 5204 signals through the second IF stage 5206. In the third frequency conversion stage 5208 the I and Q signals are transformed into I′, {overscore (I)}, Q, and {overscore (Q)} signals. This alternate embodiment of the invention relies on a “three-stage poly phase” 5210 to provide image cancellation. The advantage of using a gyrator in place of dual LC filter bank 5212 is that a close relationship between I and Q tends to be maintained throughout the circuit. The phase relationship at the output of the gyrator filter tends to be very close to 90°. If an LC filter is utilized there is no cross-coupling to maintain the phase relationship as in the gyrator. In the LC filter configuration complete reliance upon phase and amplitude matching is relied upon to maintain the I and Q signal integrity. The gyrator circuit has the additional advantage of tending to improve the phase relationship of signals initially presented to it that are not exactly in quadrature phase. For example, an I signal that is initially presented to the gyrator that is 80° out of phase with its Q component has the phase relation continuously improved throughout the gyrator such that when the signals exit the gyrator quadrature phase of 90° tends to be established between the I and Q signals, such as in a polyphase circuit element. This present embodiment of the invention provides the additional benefit of being easily integrated onto a CMOS substrate since the gyrator eliminates the inductors that an LC filter would require. Filter timing and frequency generation utilize the methods previously described.

<figref idref="DRAWINGS">FIG. 52</figref> shows a third alternate embodiment of the invention that tends to provide continuous tuning of the filter over temperature, and tends to more accurately keeps the response curve of the filter centered on the desired frequency. This embodiment of the invention preserves the separation of I 5202 and Q 5204 signals through the second IF stage 5206. In the third frequency conversion stage 5208 the I and Q signals are transformed into I′, <o ostyle="single">I</o>, Q, and <o ostyle="single">Q</o> signals. This alternate embodiment of the invention relies on a “three-stage poly phase” 5210 to provide image cancellation. The advantage of using a gyrator in place of dual LC filter bank 5212 is that a close relationship between I and Q tends to be maintained throughout the circuit. The phase relationship at the output of the gyrator filter tends to be very close to 90°. If an LC filter is utilized there is no cross-coupling to maintain the phase relationship as in the gyrator. In the LC filter configuration complete reliance upon phase and amplitude matching is relied upon to maintain the I and Q signal integrity. The gyrator circuit has the additional advantage of tending to improve the phase relationship of signals initially presented to it that are not exactly in quadrature phase. For example, an I signal that is initially presented to the gyrator that is 80° out of phase with its Q component has the phase relation continuously improved throughout the gyrator such that when the signals exit the gyrator quadrature phase of 90° tends to be established between the I and Q signals, such as in a polyphase circuit element. This present embodiment of the invention provides the additional benefit of being easily integrated onto a CMOS substrate since the gyrator eliminates the inductors that an LC filter would require. Filter timing and frequency generation utilize the methods previously described.

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<?in-line-formulae description="In-line Formulae" end="lead"?>MAG=MSG(K−√{square root over (K2−1)}) (16) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>MAG=MSG(K−√{square root over (K2−1)}) (16) <?in-line-formulae description="In-line Formulae" end="tail"?>

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<entry>{overscore (% variation in dart impact)}</entry>

<entry> <o ostyle="single">% variation in dart impact</o></entry>

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To consider the effect of DC bus disturbances on the load voltage, a linearized version of the inverter and modulator was developed from Eqn. 6 and a Taylor series expansion around the rated operating point of Eqn. 7. The inputs of x1, x2, and x3 are V*inv(t), Vdc(t), and Vd<sub2>—</sub2>filt(t), respectively, and nominal operating conditions are V*invo, Vdco, Vd<sub2>—</sub2>filto, represented by {overscore (x)}1, {overscore (x)}2, x3. The resulting linearized inverter modulator 48, Eqn. 8, is also shown in block diagram in <figref idref="DRAWINGS">FIG. 4</figref>.

To consider the effect of DC bus disturbances on the load voltage, a linearized version of the inverter and modulator was developed from Eqn. 6 and a Taylor series expansion around the rated operating point of Eqn. 7. The inputs of x1, x2, and x3 are V*inv(t), Vdc(t), and Vd<sub2>—</sub2>filt(t), respectively, and nominal operating conditions are V*invo, Vdco, Vd<sub2>—</sub2>filto, represented by <o ostyle="single">x</o>1, <o ostyle="single">x</o>2, x3. The resulting linearized inverter modulator 48, Eqn. 8, is also shown in block diagram in <figref idref="DRAWINGS">FIG. 4</figref>.

\\QA012\C$\REDBOOK_VERIFICATION\RAWCOMPAREDATA\PROD_011107-XML\US20070007998A1-20070111.XML	\\QA012\C$\REDBOOK_VERIFICATION\RAWCOMPAREDATA\TEST_011107-XML\US20070007998A1-20070111.XML

FPGA1 100, in the absence of receiving a low logic level assertion on its NPROGRAM 103 input, responds to system power-up by causing transitions on both NINIT 106 and DONE 105 outputs, to low and high logic levels, respectively. Waveform representations of NPROGRAM 202, NINIT 203, and DONE 204 are shown in <figref idref="DRAWINGS">FIG. 2</figref>. (NINIT and NPROGRAM in this writing correspond respectively to {overscore (INIT)} and {overscore (PROGRAM)} in some Xilinx FPGA documentation.)

FPGA1 100, in the absence of receiving a low logic level assertion on its NPROGRAM 103 input, responds to system power-up by causing transitions on both NINIT 106 and DONE 105 outputs, to low and high logic levels, respectively. Waveform representations of NPROGRAM 202, NINIT 203, and DONE 204 are shown in <figref idref="DRAWINGS">FIG. 2</figref>. (NINIT and NPROGRAM in this writing correspond respectively to <o ostyle="single">INIT</o> and <o ostyle="single">PROGRAM</o> in some Xilinx FPGA documentation.)

\\QA012\C$\REDBOOK_VERIFICATION\RAWCOMPAREDATA\PROD_011107-XML\US20070008004A1-20070111.XML	\\QA012\C$\REDBOOK_VERIFICATION\RAWCOMPAREDATA\TEST_011107-XML\US20070008004A1-20070111.XML

<?in-line-formulae description="In-line Formulae" end="lead"?>VT=VT(0)+γ{√{square root over (2φF−vBS)}−√{square root over (2φF)}}. (1) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>VT=VT(0)+γ{√{square root over (2φF−vBS)}−√{square root over (2φF)}}. (1) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>VT=VT(0)γ{√{square root over (2φF+vSB)}−√{square root over (2φF)}}, (2) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>VT=VT(0)γ{√{square root over (2φF+vSB)}−√{square root over (2φF)}}, (2) <?in-line-formulae description="In-line Formulae" end="tail"?>

\\QA012\C$\REDBOOK_VERIFICATION\RAWCOMPAREDATA\PROD_011107-XML\US20070008040A1-20070111.XML	\\QA012\C$\REDBOOK_VERIFICATION\RAWCOMPAREDATA\TEST_011107-XML\US20070008040A1-20070111.XML

A decoder circuit 15 is additionally provided in the digital phase detector. The inputs 150, 151, 152 to 15m of the decoder circuit are connected, on the input side, to data outputs of the flip-flop circuits F1, F2, F3 to Fm. However, provision is made in this case for the inverted output {overscore (Q)} of each second flip-flop F1, F3 to Fm−1 to be connected to the decoder inputs 150, 152 to 15m−1. In a corresponding manner, the data outputs Q of the other flip-flops F2, F4 to Fm are connected to the inputs 151, 153 to 15m of the decoder circuit 15. The inverted data output {overscore (Q)} and the normal data output Q are thus alternately connected to the decoder circuit 15 beginning with the first flip-flop circuit F1.

A decoder circuit 15 is additionally provided in the digital phase detector. The inputs 150, 151, 152 to 15m of the decoder circuit are connected, on the input side, to data outputs of the flip-flop circuits F1, F2, F3 to Fm. However, provision is made in this case for the inverted output <o ostyle="single">Q</o> of each second flip-flop F1, F3 to Fm−1 to be connected to the decoder inputs 150, 152 to 15m−1. In a corresponding manner, the data outputs Q of the other flip-flops F2, F4 to Fm are connected to the inputs 151, 153 to 15m of the decoder circuit 15. The inverted data output <o ostyle="single">Q</o> and the normal data output Q are thus alternately connected to the decoder circuit 15 beginning with the first flip-flop circuit F1.

\\QA012\C$\REDBOOK_VERIFICATION\RAWCOMPAREDATA\PROD_011107-XML\US20070008100A1-20070111.XML	\\QA012\C$\REDBOOK_VERIFICATION\RAWCOMPAREDATA\TEST_011107-XML\US20070008100A1-20070111.XML

305Enable=310Enable=303Q AND 308 {overscore (Q)},

305Enable=310Enable=303Q AND 308 <o ostyle="single">Q</o>,

where 313Q0, 313Q1, . . . , 313Q7 are, respectively, the ouput bit0 to bit7 (not shown in the figure) of the divider 313; 303Q is the sensing pulse output b of the mono-stable multi-vibrator 303; 308Q and 308 {overscore (Q)} are the setting pulse outputs of the mono-stable multi-vibrator 308; 305Reset and 306Reset are the Reset inputs of the counters 305 and 310, while 305Enable and 310Enable are the Enable inputs which enable the counting; DisplayLatch is a control signal line that can be used to latch the digital output signals into the display register. In this example, a falling edge signal is provided for the DisplayLatch. (A rising edge signal can be obtained through an inverter.)

where 313Q0, 313Q1, . . . , 313Q7 are, respectively, the ouput bit0 to bit7 (not shown in the figure) of the divider 313; 303Q is the sensing pulse output b of the mono-stable multi-vibrator 303; 308Q and 308 <o ostyle="single">Q</o> are the setting pulse outputs of the mono-stable multi-vibrator 308; 305Reset and 306Reset are the Reset inputs of the counters 305 and 310, while 305Enable and 310Enable are the Enable inputs which enable the counting; DisplayLatch is a control signal line that can be used to latch the digital output signals into the display register. In this example, a falling edge signal is provided for the DisplayLatch. (A rising edge signal can be obtained through an inverter.)

\\QA012\C$\REDBOOK_VERIFICATION\RAWCOMPAREDATA\PROD_011107-XML\US20070008202A1-20070111.XML	\\QA012\C$\REDBOOK_VERIFICATION\RAWCOMPAREDATA\TEST_011107-XML\US20070008202A1-20070111.XML

The coefficients of this polynomial Y(k) for the individual terms Y1, Y2 and Y3 determine the taps in the output circuit and in the network. Hence, in this embodiment, the coefficients (+1, +1 −1, +1 −2 +1) are obtained for a third-order modulator. This gives the tap 893, which represents the coefficient +1 for the output signal Y1(k) from the first modulator stage. The coefficient +1 for the second term is formed by the tap 892. The second coefficient −1 for the second term Y2(k) is given by the inverting output {overscore (Q)} of the last flipflop 832. Accordingly, the taps 891, 896 and 895 determine the coefficients +1 −2 and +1 for the third summand Y3(k). The additional multiplication factor in the coefficient −2 is obtained, as illustrated, through the split shown in the tap 896.

The coefficients of this polynomial Y(k) for the individual terms Y1, Y2 and Y3 determine the taps in the output circuit and in the network. Hence, in this embodiment, the coefficients (+1, +1 −1, +1 −2 +1) are obtained for a third-order modulator. This gives the tap 893, which represents the coefficient +1 for the output signal Y1(k) from the first modulator stage. The coefficient +1 for the second term is formed by the tap 892. The second coefficient −1 for the second term Y2(k) is given by the inverting output <o ostyle="single">Q</o> of the last flipflop 832. Accordingly, the taps 891, 896 and 895 determine the coefficients +1 −2 and +1 for the third summand Y3(k). The additional multiplication factor in the coefficient −2 is obtained, as illustrated, through the split shown in the tap 896.

\\QA012\C$\REDBOOK_VERIFICATION\RAWCOMPAREDATA\PROD_011107-XML\US20070008310A1-20070111.XML	\\QA012\C$\REDBOOK_VERIFICATION\RAWCOMPAREDATA\TEST_011107-XML\US20070008310A1-20070111.XML

If light distribution function LVF is a function only of the cosine of angle ζ, then LVF(ζ)={overscore (LVF)}[cos(ζ)]. Lighting intensity LI is then a function only of angle θ between the normal vector and the direction vector. Lighting intensity LI=LI(θ) is calculated for a surface element using suitable coordinates. These coordinates are preferably spherical polar coordinates (η, φ). The polar coordinates are preferably oriented in such a way that the given direction vector and the normal vector lie on the equator (θ=0) and the given direction vector additionally lies on the 0-meridian (φ=0). In that case, cos(ζ)=cos(φ)·cos(θ). If angles θ, θ, and Φ are given in arc dimensions, the lighting intensity is then calculated according to the formula:

If light distribution function LVF is a function only of the cosine of angle ζ, then LVF(ζ)= <o ostyle="single">LVF</o>[cos(ζ)]. Lighting intensity LI is then a function only of angle θ between the normal vector and the direction vector. Lighting intensity LI=LI(θ) is calculated for a surface element using suitable coordinates. These coordinates are preferably spherical polar coordinates (η, φ). The polar coordinates are preferably oriented in such a way that the given direction vector and the normal vector lie on the equator (θ=0) and the given direction vector additionally lies on the 0-meridian (φ=0). In that case, cos(ζ)=cos(φ)·cos(θ). If angles θ, θ, and Φ are given in arc dimensions, the lighting intensity is then calculated according to the formula:

Light distribution function LVF and highlight scattering function GSF are preferably functions only of the cosine of angle ζ and/or σ. It then holds that LVF(ζ)N={overscore (LVF)}[cos(ζ)] and GSF(σ)={overscore (GSF)}[cos(σ)]. These two functions may be simplified as follows with the help of the formulas that are valid in the polar coordinates introduced above. It holds that: cos(ζ)=cos(θ)cos(φ) and cos(σ)=cos(θ)·cos(φ−θ). Highlight function GF is calculated according to the following formula:

Light distribution function LVF and highlight scattering function GSF are preferably functions only of the cosine of angle ζ and/or σ. It then holds that LVF(ζ)N= <o ostyle="single">LVF</o>[cos(ζ)] and GSF(σ)= <o ostyle="single">GSF</o>[cos(σ)]. These two functions may be simplified as follows with the help of the formulas that are valid in the polar coordinates introduced above. It holds that: cos(ζ)=cos(θ)cos(φ) and cos(σ)=cos(θ)·cos(φ−θ). Highlight function GF is calculated according to the following formula:

\\QA012\C$\REDBOOK_VERIFICATION\RAWCOMPAREDATA\PROD_011107-XML\US20070008312A1-20070111.XML	\\QA012\C$\REDBOOK_VERIFICATION\RAWCOMPAREDATA\TEST_011107-XML\US20070008312A1-20070111.XML

{double overscore (I)} is a box filter smoothing operation on Ix and Iy.

<o ostyle="double">I</o> is a box filter smoothing operation on Ix and Iy.

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wherein N is the number of pixels in the subframe, and ΔHuei=Huei;−{overscore (Huei)};if ΔHuei;>180 then ΔHuei=360−ΔHuei

wherein N is the number of pixels in the subframe, and ΔHuei=Huei;− <o ostyle="single">Huei</o>;if ΔHuei;>180 then ΔHuei=360−ΔHuei

wherein N is the number of pixels in the subframe, and ΔHuei=Huei;−{overscore (Huei)};if ΔHuei;>48 then ΔHuei=96−ΔHuei

wherein N is the number of pixels in the subframe, and ΔHuei=Huei;− <o ostyle="single">Huei</o>;if ΔHuei;>48 then ΔHuei=96−ΔHuei

\\QA012\C$\REDBOOK_VERIFICATION\RAWCOMPAREDATA\PROD_011107-XML\US20070008551A1-20070111.XML	\\QA012\C$\REDBOOK_VERIFICATION\RAWCOMPAREDATA\TEST_011107-XML\US20070008551A1-20070111.XML

Where a is the background intensity, N is the total number of temporal intensity samples, m is the function representing the fringe modulation or envelope for the subject pixel of the sample, τ is the position effected by means of the pusher 50 producing the temporal sample intensity frame having the peak of the intensity envelope, n is the position effected by means of the pusher 50 to produce the selected temporal sample intensity frame, also known as the frame number, {overscore (ω)}s is the phase shift, and φ carries the height information of the measuring surfaces. Thus, when n==τ, the modulation is maximum.

Where a is the background intensity, N is the total number of temporal intensity samples, m is the function representing the fringe modulation or envelope for the subject pixel of the sample, τ is the position effected by means of the pusher 50 producing the temporal sample intensity frame having the peak of the intensity envelope, n is the position effected by means of the pusher 50 to produce the selected temporal sample intensity frame, also known as the frame number, <o ostyle="single">ω</o>s is the phase shift, and φ carries the height information of the measuring surfaces. Thus, when n==τ, the modulation is maximum.

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<?in-line-formulae description="In-line Formulae" end="lead"?>{overscore (q)}n−1,j)=q(n−1,j. (4)<?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?> <o ostyle="single">q</o>n−1,j)=q(n−1,j. (4)<?in-line-formulae description="In-line Formulae" end="tail"?>

\\QA012\C$\REDBOOK_VERIFICATION\RAWCOMPAREDATA\PROD_011107-XML\US20070009004A1-20070111.XML	\\QA012\C$\REDBOOK_VERIFICATION\RAWCOMPAREDATA\TEST_011107-XML\US20070009004A1-20070111.XML

where the oxygen is in its lowest energy electronically excited state, O2(a1Δg). For convenience, this is referred to as singlet delta oxygen or as O2(1Δ). Normally, oxygen is in its electronic ground state, O2(X3Σ{overscore (g)}), which, hereafter, is written as O2(3Σ) or just O2. In Reaction A, the chlorine vapor diffuses into the aqueous BHP solution, forming potassium chloride (KCI), or sodium chloride (NaCl) if NaOH is used in the reaction, water, and O2(1Δ). The O2(1Δ) can form bubbles and diffuse out of the solution. The presence of singlet delta oxygen from the reaction of BHP and chlorine in Reaction A is evident by a red dimol emission (see “Direct Spectroscopic Evidence for a Deuterium Solvent Effect on the Lifetime of Singlet Delta Oxygen in Water,” Kajiwara and Kearns, Journal of the American Chemical Society, vol. 95, No. 18, pp. 5886-5890, September 1973) that is visible by sight. This emission stems from the chemiluminescence of (O2(a1Δ))2.

where the oxygen is in its lowest energy electronically excited state, O2(a1Δg). For convenience, this is referred to as singlet delta oxygen or as O2(1Δ). Normally, oxygen is in its electronic ground state, O2(X3Σ <o ostyle="single">g</o>), which, hereafter, is written as O2(3Σ) or just O2. In Reaction A, the chlorine vapor diffuses into the aqueous BHP solution, forming potassium chloride (KCI), or sodium chloride (NaCl) if NaOH is used in the reaction, water, and O2(1Δ). The O2(1Δ) can form bubbles and diffuse out of the solution. The presence of singlet delta oxygen from the reaction of BHP and chlorine in Reaction A is evident by a red dimol emission (see “Direct Spectroscopic Evidence for a Deuterium Solvent Effect on the Lifetime of Singlet Delta Oxygen in Water,” Kajiwara and Kearns, Journal of the American Chemical Society, vol. 95, No. 18, pp. 5886-5890, September 1973) that is visible by sight. This emission stems from the chemiluminescence of (O2(a1Δ))2.

\\QA012\C$\REDBOOK_VERIFICATION\RAWCOMPAREDATA\PROD_011107-XML\US20070009013A1-20070111.XML	\\QA012\C$\REDBOOK_VERIFICATION\RAWCOMPAREDATA\TEST_011107-XML\US20070009013A1-20070111.XML

Since channelization codes are employed for user separation and scrambling codes are employed for cell separation, the channelization code and scrambling codes are known a priori according to cell location and are transmitted to a respective user from a cell base station via a learning transmission. The learning transmission is beyond the scope of this disclosure. M channelization codes are available for use, {tilde over (c)}i . . . {tilde over (c)}M<sub2>1</sub2>,cM1+1 . . . cMof which the first M1 are complex and the remaining are real. The nth element of the ith complex channelization code is defined as:

Since channelization codes are employed for user separation and scrambling codes are employed for cell separation, the channelization code and scrambling codes are known a priori according to cell location and are transmitted to a respective user from a cell base station via a learning transmission. The learning transmission is beyond the scope of this disclosure. M channelization codes are available for use, {tilde over (c)}i . . . {tilde over (c)}M<sub2>1</sub2>,cM1+1 . . . cMof which the first M1 are complex and the remaining are real. The nth element of the ith complex channelization code is defined as:

<?in-line-formulae description="In-line Formulae" end="lead"?>s[n]=cp [n]·v[n], where n=1, . . . SFmax (10) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>s[n]=cp [n]·v[n], where n=1, . . . SFmax (10) <?in-line-formulae description="In-line Formulae" end="tail"?>

where cp, is a product of the periodic extensions of the subchannel k channelization codes c, containing N periods of c corresponding to the spreading factor SF. Intermediate real code s of length SFmax is computed (step 103) using v and c and is made up of M+P real codes.

where cp, is a product of the periodic extensions of the subchannel k channelization codes c, containing N periods of c corresponding to the spreading factor SF. Intermediate real code s of length SFmax is computed (step 103) using v and c and is made up of M+P real codes.

\\QA012\C$\REDBOOK_VERIFICATION\RAWCOMPAREDATA\PROD_011107-XML\US20070009018A1-20070111.XML	\\QA012\C$\REDBOOK_VERIFICATION\RAWCOMPAREDATA\TEST_011107-XML\US20070009018A1-20070111.XML

In the following description and in the accompanying drawings, specific terminology and drawing symbols are set forth to provide a thorough understanding of the present invention. In some instances, the terminology and symbols may imply specific details that are not required to practice the invention. For example, the interconnection between circuit elements or circuit blocks may be shown or described as multi-conductor or single conductor signal lines. Each of the multi-conductor signal lines may alternatively be single-conductor signal lines, and each of the single-conductor signal lines may alternatively be multi-conductor signal lines. Signals and signaling paths shown or described as being single-ended may also be differential, and vice-versa. Similarly, signals described or depicted as having active-high or active-low logic levels may have opposite logic levels in alternative embodiments. As another example, circuits described or depicted as including metal oxide semiconductor (MOS) transistors may alternatively be implemented using bipolar technology or any other technology in which a signal-controlled current flow may be achieved. With respect to terminology, a signal is said to be “asserted” when the signal is driven to a low or high logic state (or charged to a high logic state or discharged to a low logic state) to indicate a particular condition. Conversely, a signal is said to be “deasserted” to indicate that the signal is driven (or charged or discharged) to a state other than the asserted state (including a high or low logic state, or the floating state that may occur when the signal driving circuit is transitioned to a high impedance condition, such as an open drain or open collector condition). A signal driving circuit is said to “output” a signal to a signal receiving circuit when the signal driving circuit asserts (or deasserts, if explicitly stated or indicated by context) the signal on a signal line coupled between the signal driving and signal receiving circuits. A signal line is said to be “activated” when a signal is asserted on the signal line, and “deactivated” when the signal is deasserted. Additionally, the prefix symbol “/” attached to signal names indicates that the signal is an active low signal (i.e., the asserted state is a logic low state). A line over a signal name (e.g., ‘{overscore (<signal name>)}’) is also used to indicate an active low signal. The term “coupled” is used herein to express a direct connection as well as a connection through one or more intervening circuits or structures. The term “exemplary” is used to express an example, not a preference or requirement.

In the following description and in the accompanying drawings, specific terminology and drawing symbols are set forth to provide a thorough understanding of the present invention. In some instances, the terminology and symbols may imply specific details that are not required to practice the invention. For example, the interconnection between circuit elements or circuit blocks may be shown or described as multi-conductor or single conductor signal lines. Each of the multi-conductor signal lines may alternatively be single-conductor signal lines, and each of the single-conductor signal lines may alternatively be multi-conductor signal lines. Signals and signaling paths shown or described as being single-ended may also be differential, and vice-versa. Similarly, signals described or depicted as having active-high or active-low logic levels may have opposite logic levels in alternative embodiments. As another example, circuits described or depicted as including metal oxide semiconductor (MOS) transistors may alternatively be implemented using bipolar technology or any other technology in which a signal-controlled current flow may be achieved. With respect to terminology, a signal is said to be “asserted” when the signal is driven to a low or high logic state (or charged to a high logic state or discharged to a low logic state) to indicate a particular condition. Conversely, a signal is said to be “deasserted” to indicate that the signal is driven (or charged or discharged) to a state other than the asserted state (including a high or low logic state, or the floating state that may occur when the signal driving circuit is transitioned to a high impedance condition, such as an open drain or open collector condition). A signal driving circuit is said to “output” a signal to a signal receiving circuit when the signal driving circuit asserts (or deasserts, if explicitly stated or indicated by context) the signal on a signal line coupled between the signal driving and signal receiving circuits. A signal line is said to be “activated” when a signal is asserted on the signal line, and “deactivated” when the signal is deasserted. Additionally, the prefix symbol “/” attached to signal names indicates that the signal is an active low signal (i.e., the asserted state is a logic low state). A line over a signal name (e.g., ‘ <o ostyle="single"><signal name></o>’) is also used to indicate an active low signal. The term “coupled” is used herein to express a direct connection as well as a connection through one or more intervening circuits or structures. The term “exemplary” is used to express an example, not a preference or requirement.

\\QA012\C$\REDBOOK_VERIFICATION\RAWCOMPAREDATA\PROD_011107-XML\US20070009066A1-20070111.XML	\\QA012\C$\REDBOOK_VERIFICATION\RAWCOMPAREDATA\TEST_011107-XML\US20070009066A1-20070111.XML

The invention represents a parallel and distributed approach to clock recovery. The clock recovery mechanism proposed by the invention operates based on multiple mutually phase shifted sample clock signals defining a set of orthogonal clock phases. Using the mathematical concepts of vectors and orthogonal systems in linear spaces, a vector-based notation is introduced to fully disclose the parallelism in the clock recovery algorithm. With reference to <figref idref="DRAWINGS">FIG. 1</figref>, the mutually phase shifted clock signals, forming a multiphase sample clock vector ({overscore (S)}), are employed for sampling an input data signal D to obtain an input data sample vector ({overscore (U)}). In general, each input data sample element in the vector ({overscore (U)}) is only updated once during the sample clock cycle (period) associated with that particular sample element. Input data transition detection is represented by a transform designed to identify and uniquely sort out an input data signal transition and to algorithmically associate it with a suitable sample clock phase in the vicinity of the transition. This is preferably accomplished by determining, for each one of the above clock phases, whether input data samples within a detection window associated with the respective clock phase includes an input data transition, thus generating an input data transition vector ({overscore (TR)}). The output clock is dynamically selected from the ensemble of mutually exclusive sample clocks, initially triggered by an input data signal transition. Therefore, a corresponding clock selection control signal vector ({overscore (SEL)}) is generated based on the input data transition vector ({overscore (TR)}) to determine a clock selection master. The selection of a new sample clock phase is preferably performed in such a manner that there is a self-appointed dynamic clock selection master controlling the output clock until a new input data transition triggers another clock selection master. In order to dynamically extract an output clock signal, the control signal vector ({overscore (SEL)}) is logically combined with a representation ({overscore (S′)}), preferably a rotated version, of the sample clock vector ({overscore (S)}). The dynamic clock master control and output clock extraction may thus ultimately be reduced to a simple combinatorial logical combination task, preferably performed in parallel and in much resembling a simple scalar product operation, involving the control signal vector and the rotated multiphase sample clock vector.

The invention represents a parallel and distributed approach to clock recovery. The clock recovery mechanism proposed by the invention operates based on multiple mutually phase shifted sample clock signals defining a set of orthogonal clock phases. Using the mathematical concepts of vectors and orthogonal systems in linear spaces, a vector-based notation is introduced to fully disclose the parallelism in the clock recovery algorithm. With reference to <figref idref="DRAWINGS">FIG. 1</figref>, the mutually phase shifted clock signals, forming a multiphase sample clock vector ( <o ostyle="single">S</o>), are employed for sampling an input data signal D to obtain an input data sample vector ( <o ostyle="single">U</o>). In general, each input data sample element in the vector ( <o ostyle="single">U</o>) is only updated once during the sample clock cycle (period) associated with that particular sample element. Input data transition detection is represented by a transform designed to identify and uniquely sort out an input data signal transition and to algorithmically associate it with a suitable sample clock phase in the vicinity of the transition. This is preferably accomplished by determining, for each one of the above clock phases, whether input data samples within a detection window associated with the respective clock phase includes an input data transition, thus generating an input data transition vector ( <o ostyle="single">TR</o>). The output clock is dynamically selected from the ensemble of mutually exclusive sample clocks, initially triggered by an input data signal transition. Therefore, a corresponding clock selection control signal vector ( <o ostyle="single">SEL</o>) is generated based on the input data transition vector ( <o ostyle="single">TR</o>) to determine a clock selection master. The selection of a new sample clock phase is preferably performed in such a manner that there is a self-appointed dynamic clock selection master controlling the output clock until a new input data transition triggers another clock selection master. In order to dynamically extract an output clock signal, the control signal vector ( <o ostyle="single">SEL</o>) is logically combined with a representation ( <o ostyle="single">S′</o>), preferably a rotated version, of the sample clock vector ( <o ostyle="single">S</o>). The dynamic clock master control and output clock extraction may thus ultimately be reduced to a simple combinatorial logical combination task, preferably performed in parallel and in much resembling a simple scalar product operation, involving the control signal vector and the rotated multiphase sample clock vector.

Each sample phase, Si, has an associated transition detector, TRi, which operates on the sampled (and held) representation of the input data signal, U1 . . . UN. Note that the transition detection is unique and only one transition indicator, TRi, is high at a time even if the sampled data vector, {overscore (U)}, may contain several or a mix of ones and zeros.

Each sample phase, Si, has an associated transition detector, TRi, which operates on the sampled (and held) representation of the input data signal, U1 . . . UN. Note that the transition detection is unique and only one transition indicator, TRi, is high at a time even if the sampled data vector, <o ostyle="single">U</o>, may contain several or a mix of ones and zeros.

In addition to the basic building blocks mentioned in connection with <figref idref="DRAWINGS">FIG. 2</figref>, the clock recovery system 100 is now illustrated with a phase shift unit 7, also denoted PHSU, for generating the sample clocks, S1 . . . SN, e.g. by decoding a high frequency divider or using a delay locked loop. The clock recovery system is also illustrated as having a data sampling unit 9, also denoted DSU, for sampling the input data signal, DATA IN, to extract a time discrete representation, U1 . . . UN, of the input data signal by means of the set {overscore (S)} of phase shifted sample clocks. The phase shift unit 7 and the data sampling unit 9 may, if desired, be considered as external modules and are presented shaded in <figref idref="DRAWINGS">FIG. 6</figref>.

In addition to the basic building blocks mentioned in connection with <figref idref="DRAWINGS">FIG. 2</figref>, the clock recovery system 100 is now illustrated with a phase shift unit 7, also denoted PHSU, for generating the sample clocks, S1 . . . SN, e.g. by decoding a high frequency divider or using a delay locked loop. The clock recovery system is also illustrated as having a data sampling unit 9, also denoted DSU, for sampling the input data signal, DATA IN, to extract a time discrete representation, U1 . . . UN, of the input data signal by means of the set <o ostyle="single">S</o> of phase shifted sample clocks. The phase shift unit 7 and the data sampling unit 9 may, if desired, be considered as external modules and are presented shaded in <figref idref="DRAWINGS">FIG. 6</figref>.

<?in-line-formulae description="In-line Formulae" end="lead"?>Ui≠Uj|jεSW<?img id="custom-character-00001" he="3.13mm" wi="3.13mm" file="US20070009066A1-20070111-P00001.TIF" alt="custom character" img-content="character" img-format="tif" ?>Ui·{overscore (U)}j+{overscore (U)}i·Uj=Ui⊕Uj=1 (Eq. 3) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>Ui≠Uj|jεSW<?img id="custom-character-00001" he="3.13mm" wi="3.13mm" file="US20070009066A1-20070111-P00001.TIF" alt="custom character" img-content="character" img-format="tif" ?>Ui· <o ostyle="single">U</o>j+ <o ostyle="single">U</o>i·Uj=Ui⊕Uj=1 (Eq. 3) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>TRi=(Ui⊕Ui+1+Ui−1⊕Ui+1)·{overscore ((Ui⊕Ui−1))} (Eq. 4) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>TRi=(Ui⊕Ui+1+Ui−1⊕Ui+1)· <o ostyle="single">(Ui⊕Ui−1)</o> (Eq. 4) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>{overscore (Ui−1⊕Ui)} (Eq. 5) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?> <o ostyle="single">Ui−1⊕Ui</o> (Eq. 5) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>TRi={overscore (U)}i−1·{overscore (U)}i·Ui+1+Ui−1·Ui·{overscore (U)}i+1 (Eq. 6) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>TRi= <o ostyle="single">U</o>i−1· <o ostyle="single">U</o>i·Ui+1+Ui−1·Ui· <o ostyle="single">U</o>i+1 (Eq. 6) <?in-line-formulae description="In-line Formulae" end="tail"?>

All transition conditions are only updated once in a sample clock period coincident with the associated store pulse or clock transition, SSTO, when all comprising parts of the sampled input data representation, {overscore (U)}, are refreshed and the overall expression is stable. Normally the transition condition is set coincident with the first consecutive sample clock transition for the clock phase outside the detection window, i.e. i+2 in the preferred embodiment. As seen above several reset conditions exist. One important feature is to utilize the asynchronous transition indicator output signal, ASY TR or ATR in short, to clear all transition indications that stem from the prior input data transition. Proper start up behavior for the entire clock recovery unit is also ensured when the asynchronous reset signal clear all synchronous transition indicators after a new input data signal transition has occurred. Logic race conditions, combinatorial loops and dead lock situations are effectively avoided and the latency is minimized. Without explicit interaction or hand shake procedures between the transition indicator and the clock mux control unit in order to communicate a transition indication and thereby not relaying on an fixed reset clock phase, SRES, given a priori every indication that has not been detected must be cleared before the new clock phase selection can be performed. For instance in an asynchronous communication manner the transition detector may raise its condition coincident with the store pulse once the condition is valid but is forced to await that the corresponding clock mux control unit state machine has transitioned into the request state (01b) before a reset is performed. Asynchronous communication between the transition indicator and the clock mux control units however require a different reset condition in order to clear an occupied pre indication state after a new input data signal transition has occurred. In <figref idref="DRAWINGS">FIG. 10</figref>, the alternative transition condition including asynchronous reset, AR connected to ASY TR, is shown. Close examination of the transition indicator state machine operation particularly when the transition condition is evaluated reveals that the operation indeed is edge triggered and that the transition condition is sampled coincident with the store pulse or sample clock transition outside the detection window. At any time prior to the store operation a false transition condition output from the combinatorial net inevitably reset the transition indicator state machine back into the initial state (00b), where there is no direct transition path to the valid transition detection output state (11b). A valid transition condition, i.e. TRi goes high, only give a possible transition detection if it appear when the store signal is low for a positively edge triggered transition indicator. Thereby a latching behavior is avoided and the transition indicator may not be set on multiple occasions during a single store pulse duration.

All transition conditions are only updated once in a sample clock period coincident with the associated store pulse or clock transition, SSTO, when all comprising parts of the sampled input data representation, <o ostyle="single">U</o>, are refreshed and the overall expression is stable. Normally the transition condition is set coincident with the first consecutive sample clock transition for the clock phase outside the detection window, i.e. i+2 in the preferred embodiment. As seen above several reset conditions exist. One important feature is to utilize the asynchronous transition indicator output signal, ASY TR or ATR in short, to clear all transition indications that stem from the prior input data transition. Proper start up behavior for the entire clock recovery unit is also ensured when the asynchronous reset signal clear all synchronous transition indicators after a new input data signal transition has occurred. Logic race conditions, combinatorial loops and dead lock situations are effectively avoided and the latency is minimized. Without explicit interaction or hand shake procedures between the transition indicator and the clock mux control unit in order to communicate a transition indication and thereby not relaying on an fixed reset clock phase, SRES, given a priori every indication that has not been detected must be cleared before the new clock phase selection can be performed. For instance in an asynchronous communication manner the transition detector may raise its condition coincident with the store pulse once the condition is valid but is forced to await that the corresponding clock mux control unit state machine has transitioned into the request state (01b) before a reset is performed. Asynchronous communication between the transition indicator and the clock mux control units however require a different reset condition in order to clear an occupied pre indication state after a new input data signal transition has occurred. In <figref idref="DRAWINGS">FIG. 10</figref>, the alternative transition condition including asynchronous reset, AR connected to ASY TR, is shown. Close examination of the transition indicator state machine operation particularly when the transition condition is evaluated reveals that the operation indeed is edge triggered and that the transition condition is sampled coincident with the store pulse or sample clock transition outside the detection window. At any time prior to the store operation a false transition condition output from the combinatorial net inevitably reset the transition indicator state machine back into the initial state (00b), where there is no direct transition path to the valid transition detection output state (11b). A valid transition condition, i.e. TRi goes high, only give a possible transition detection if it appear when the store signal is low for a positively edge triggered transition indicator. Thereby a latching behavior is avoided and the transition indicator may not be set on multiple occasions during a single store pulse duration.

<?in-line-formulae description="In-line Formulae" end="lead"?>q1+=q1·q0+q1·{overscore (R)}·{overscore (AR)}+q0·T·V (Eq. 9) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>q1+=q1·q0+q1· <o ostyle="single">R</o>· <o ostyle="single">AR</o>+q0·T·V (Eq. 9) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>q0+={overscore (q)}1·q0·T+{overscore (q)}1·T·{overscore (V)} (Eq. 10) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>q0+= <o ostyle="single">q</o>1·q0·T+ <o ostyle="single">q</o>1·T· <o ostyle="single">V</o> (Eq. 10) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>ASY TR=AR=q1·{overscore (q0)}+{overscore (q1)}·q0=q1⊕q0 (Eq. 13) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>ASY TR=AR=q1· <o ostyle="single">q0</o>+ <o ostyle="single">q1</o>·q0=q1⊕q0 (Eq. 13) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>ASY TR COMB=q1·q0·{overscore (D)}+{overscore (q1)}·{overscore (q0)}·D (Eq. 14) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>ASY TR COMB=q1·q0· <o ostyle="single">D</o>+ <o ostyle="single">q1</o>· <o ostyle="single">q0</o>·D (Eq. 14) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>q1+=q1·q0+q1·{overscore (A)}+q0·A (Eq. 15) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>q1+=q1·q0+q1· <o ostyle="single">A</o>+q0·A (Eq. 15) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>q0+={overscore (q)}1·q0+{overscore (q)}1·D+q0·D (Eq. 16) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>q0+= <o ostyle="single">q</o>1·q0+ <o ostyle="single">q</o>1·D+q0·D (Eq. 16) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>q1+=q1·q0·{overscore (AR)}+q0REL·{overscore (AR)}+q1·{overscore (R)} (Eq. 17) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>q1+=q1·q0· <o ostyle="single">AR</o>+q0REL· <o ostyle="single">AR</o>+q1· <o ostyle="single">R</o> (Eq. 17) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>q0+={overscore (q)}1·q0·{overscore (AR)}+q1·q0·AR+{overscore (q)}1·TRi·{overscore (AR)}+q0·REQ·{overscore (AR)}(Eq. 18) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>q0+= <o ostyle="single">q</o>1·q0· <o ostyle="single">AR</o>+q1·q0·AR+ <o ostyle="single">q</o>1·TRi· <o ostyle="single">AR</o>+q0·REQ· <o ostyle="single">AR</o>(Eq. 18) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>REQi={overscore (q)}1·q0 (Eq. 19) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>REQi= <o ostyle="single">q</o>1·q0 (Eq. 19) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>RELi={overscore (q1·{double overscore (q)}0+q1·q0 )} (Eq. 20) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>RELi= <o ostyle="single">q1·</o> <o ostyle="double">q</o> <o ostyle="single">0+q1·q0 </o> (Eq. 20) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>SELi=q1·{overscore (q)}0+q1·q0 (Eq. 21) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>SELi=q1· <o ostyle="single">q</o>0+q1·q0 (Eq. 21) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>{overscore (S)}U·SL=1 (Eq. 23) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?> <o ostyle="single">S</o>U·SL=1 (Eq. 23) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>CLR={overscore (SL·{double overscore (S)}U)}={overscore (S)}L+SU (Eq. 26) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>CLR= <o ostyle="single">SL·</o> <o ostyle="double">S</o> <o ostyle="single">U</o>= <o ostyle="single">S</o>L+SU (Eq. 26) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>{overscore (REQ)}·CLR={overscore (REQ)}·{overscore (SL·{double overscore (S)}U )} (Eq. 27) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?> <o ostyle="single">REQ</o>·CLR= <o ostyle="single">REQ</o>· <o ostyle="single">SL·</o> <o ostyle="double">S</o> <o ostyle="single">U </o> (Eq. 27) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>OPT(q0+)=q0 ·{overscore (REQ)}·SL·{overscore (S)}U (Eq. 28) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>OPT(q0+)=q0 · <o ostyle="single">REQ</o>·SL· <o ostyle="single">S</o>U (Eq. 28) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>q1+=q1·q0·{overscore (S)}U+q1·REQ+q0·{overscore (REQ)}·SL·{overscore (S)}U (Eq. 29) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>q1+=q1·q0· <o ostyle="single">S</o>U+q1·REQ+q0· <o ostyle="single">REQ</o>·SL· <o ostyle="single">S</o>U (Eq. 29) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>q0+=q1·q0{overscore (REQ)}+{overscore (q)}1·SL·{overscore (S)}U+q0·{overscore (REQ)}·SL·{overscore (S)}U (Eq. 30) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>q0+=q1·q0 <o ostyle="single">REQ</o>+ <o ostyle="single">q</o>1·SL· <o ostyle="single">S</o>U+q0· <o ostyle="single">REQ</o>·SL· <o ostyle="single">S</o>U (Eq. 30) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>REQf=REQf(i)=q1·{overscore (q)}0 (Eq. 31) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>REQf=REQf(i)=q1· <o ostyle="single">q</o>0 (Eq. 31) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>{overscore (SEL1)}+ . . . +{overscore (SELi−1)}+SELi+{overscore (SELi+1)}+ . . . +{overscore (SELN)}<img id="custom-character-00002" he="3.13mm" wi="3.13mm" file="US20070009066A1-20070111-P00001.TIF" alt="custom character" img-content="character" img-format="tif"/>SC=SELi·Si=Si (Eq. 40) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?> <o ostyle="single">SEL1</o>+ . . . + <o ostyle="single">SELi−1</o>+SELi+ <o ostyle="single">SELi+1</o>+ . . . + <o ostyle="single">SELN</o><?img id="custom-character-00002" he="3.13mm" wi="3.13mm" file="US20070009066A1-20070111-P00001.TIF" alt="custom character" img-content="character" img-format="tif" ?>SC=SELi·Si=Si (Eq. 40) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>SC=(S1+{overscore (SEL1)})·(S2+{overscore (SEL2)})· . . . ·(SN+{overscore (SELN)}) (Eq. 41) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>SC=(S1+ <o ostyle="single">SEL1</o>)·(S2+ <o ostyle="single">SEL2</o>)· . . . ·(SN+ <o ostyle="single">SELN</o>) (Eq. 41) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>E={overscore (q)}0·{overscore (q)}1 (Eq. 46) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>E= <o ostyle="single">q</o>0· <o ostyle="single">q</o>1 (Eq. 46) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>q1+=q1·q0+q0·{overscore (P)}+q1·{overscore (P)} (Eq. 47) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>q1+=q1·q0+q0· <o ostyle="single">P</o>+q1· <o ostyle="single">P</o> (Eq. 47) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>q0+={overscore (q)}1·q0+{overscore (q)}1·H (Eq. 48) <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>q0+= <o ostyle="single">q</o>1·q0+ <o ostyle="single">q</o>1·H (Eq. 48) <?in-line-formulae description="In-line Formulae" end="tail"?>

\\QA012\C$\REDBOOK_VERIFICATION\RAWCOMPAREDATA\PROD_011107-XML\US20070009077A1-20070111.XML	\\QA012\C$\REDBOOK_VERIFICATION\RAWCOMPAREDATA\TEST_011107-XML\US20070009077A1-20070111.XML

RF dividers based on synchronous flip-flops are well known. They consist of a chain of a number of n flip-flops clocked with opposite signals. The resulting output has 2n signals at equidistant phases with 1/n th of the input frequency. A typical standard RF flip-flop for this purpose is shown in <figref idref="DRAWINGS">FIG. 1</figref>. (In the literature exist many variations of this structure e.g. the PMOS load can be replaced by a resistor.) The flip-flop has two differential clock inputs C,{overscore (C)}, two differential inputs I,{overscore (I)}, and two differential outputs O,{overscore (O)}. The clock inputs are sensitive to the rising edge of a clock input signal.

RF dividers based on synchronous flip-flops are well known. They consist of a chain of a number of n flip-flops clocked with opposite signals. The resulting output has 2n signals at equidistant phases with 1/n th of the input frequency. A typical standard RF flip-flop for this purpose is shown in <figref idref="DRAWINGS">FIG. 1</figref>. (In the literature exist many variations of this structure e.g. the PMOS load can be replaced by a resistor.) The flip-flop has two differential clock inputs C, <o ostyle="single">C</o>, two differential inputs I, <o ostyle="single">I</o>, and two differential outputs O, <o ostyle="single">O</o>. The clock inputs are sensitive to the rising edge of a clock input signal.

<entry>{overscore (I)}</entry>

<entry>{overscore (C)}</entry>

<entry>{overscore (O)}n</entry>

<entry>{overscore (O)}n−1</entry>

<entry>{overscore (O)}n−1</entry>

The two outputs O,{overscore (O)} of one flip-flop are connected to the corresponding inputs I,{overscore (I)} of the subsequent flip-flop, respectively. The outputs O,{overscore (O)} of the endmost flip-flop are connected inversely to the inputs I,{overscore (I)} of the first flip-flop, respectively. The flip-flops are clocked at their clock inputs C,{overscore (C)} with differential clock signals in a consecutive manner. The clock signals are provided by a quadrature oscillator, having at least four quadrature outputs with equidistant phases, e.g. at 0°, 90°, 180°, and 270°. The two differential clock signals input to each flip-flop are individually selected from the quadrature outputs In_0, In_90, In_180, and In_270 of the quadrature oscillator.

The two outputs O, <o ostyle="single">O</o> of one flip-flop are connected to the corresponding inputs I, <o ostyle="single">I</o> of the subsequent flip-flop, respectively. The outputs O, <o ostyle="single">O</o> of the endmost flip-flop are connected inversely to the inputs I, <o ostyle="single">I</o> of the first flip-flop, respectively. The flip-flops are clocked at their clock inputs C, <o ostyle="single">C</o> with differential clock signals in a consecutive manner. The clock signals are provided by a quadrature oscillator, having at least four quadrature outputs with equidistant phases, e.g. at 0°, 90°, 180°, and 270°. The two differential clock signals input to each flip-flop are individually selected from the quadrature outputs In_0, In_90, In_180, and In_270 of the quadrature oscillator.

<entry>{overscore (I)}</entry>

<entry>{overscore (C)}</entry>

<entry>{overscore (O)}n</entry>

<entry>{overscore (O)}n−1</entry>

<entry>{overscore (O)}n−1</entry>

<claim-text>a plurality of flip-flops, including at least a first flip-flop and an endmost flip-flop, the flip-flops are interoperably coupled in series to produce a predetermined dividing ratio, wherein each of the plurality of flip-flops includes two differential inputs I,{overscore (I)} two differential outputs O,{overscore (O)} and two differential clock inputs C,{overscore (C)}, the outputs O,{overscore (O)} of one flip-flop are connected to the corresponding inputs I,{overscore (I)} of a subsequent flip-flop, the outputs O,{overscore (O)} of the endmost flip-flop are connected inversely to the inputs I,{overscore (I)} of the first flip-flop, wherein the flip-flops are clocked at their clock inputs C,{overscore (C)} with differential clock signals in a consecutive manner which, for each flip-flop, are individually selected from quadrature clock input signals, In_0, In_90, In_180, and In_270. </claim-text>

<claim-text>a plurality of flip-flops, including at least a first flip-flop and an endmost flip-flop, the flip-flops are interoperably coupled in series to produce a predetermined dividing ratio, wherein each of the plurality of flip-flops includes two differential inputs I, <o ostyle="single">I</o> two differential outputs O, <o ostyle="single">O</o> and two differential clock inputs C, <o ostyle="single">C</o>, the outputs O, <o ostyle="single">O</o> of one flip-flop are connected to the corresponding inputs I, <o ostyle="single">I</o> of a subsequent flip-flop, the outputs O, <o ostyle="single">O</o> of the endmost flip-flop are connected inversely to the inputs I, <o ostyle="single">I</o> of the first flip-flop, wherein the flip-flops are clocked at their clock inputs C, <o ostyle="single">C</o> with differential clock signals in a consecutive manner which, for each flip-flop, are individually selected from quadrature clock input signals, In_0, In_90, In_180, and In_270. </claim-text>

<claim-text>4. The quadrature divider of <claim-ref idref="CLM-00003">claim 3</claim-ref>, characterized in that the clock inputs C,{overscore (C)} of the n-th flip-flop are connected to the clock input signals In_0+(n−1)*90 and In_180+(n−1)*90, respectively. </claim-text>

<claim-text>4. The quadrature divider of <claim-ref idref="CLM-00003">claim 3</claim-ref>, characterized in that the clock inputs C, <o ostyle="single">C</o> of the n-th flip-flop are connected to the clock input signals In_0+(n−1)*90 and In_180+(n−1)*90, respectively. </claim-text>

<claim-text>9. The quadrature divider of <claim-ref idref="CLM-00007">claim 7</claim-ref>, characterized in that the clock inputs C,{overscore (C)} of the n-th flip-flop are connected to the clock input signals In_0+(n−1)*270 and In_180+(n−1)*270, respectively. </claim-text>

<claim-text>9. The quadrature divider of <claim-ref idref="CLM-00007">claim 7</claim-ref>, characterized in that the clock inputs C, <o ostyle="single">C</o> of the n-th flip-flop are connected to the clock input signals In_0+(n−1)*270 and In_180+(n−1)*270, respectively. </claim-text>

<claim-text>16. The quadrature divider of <claim-ref idref="CLM-00008">claim 8</claim-ref>, characterized in that the clock inputs C,{overscore (C)} of the n-th flip-flop are connected to the clock input signals In_0+(n−1)*270 and In_180+(n−1)*270, respectively. </claim-text>

<claim-text>16. The quadrature divider of <claim-ref idref="CLM-00008">claim 8</claim-ref>, characterized in that the clock inputs C, <o ostyle="single">C</o> of the n-th flip-flop are connected to the clock input signals In_0+(n−1)*270 and In_180+(n−1)*270, respectively. </claim-text>

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Thus in an embodiment of the present invention, by selecting a value of N as a key, a corresponding unique value {overscore (s)}r(A) can be found from the solution of Eq. 8.

Thus in an embodiment of the present invention, by selecting a value of N as a key, a corresponding unique value <o ostyle="single">s</o>r(A) can be found from the solution of Eq. 8.

By using this unique value {overscore (s)}r(A) as ŝr(A) 120, a watermarked image block Â dependent both upon key N via Eq. 8 and key K via Eq. 7 is produced using Â=UAŜAVAT 130, with the watermark distributed over the entire block Â through manipulation of the smallest singular value of A.

By using this unique value <o ostyle="single">s</o>r(A) as ŝr(A) 120, a watermarked image block Â dependent both upon key N via Eq. 8 and key K via Eq. 7 is produced using Â=UAŜAVAT 130, with the watermark distributed over the entire block Â through manipulation of the smallest singular value of A.

<li id="ul0002-0003" num="0074"> iii. Estimating 120 the unique parameter {overscore (s)}r(A), that minimizes the expression:

<li id="ul0002-0003" num="0074"> iii. Estimating 120 the unique parameter <o ostyle="single">s</o>r(A), that minimizes the expression:

<li id="ul0002-0005" num="0076"> iv. Estimating 130 the watermarked block Â=UAŜAVAT by setting Ŝ=diag(s1(A), . . . , sr−1(A), {overscore (s)}r(A)). </li>

In an otherwise similar enhanced embodiment of the present invention, step iii. above comprises estimating the unique parameter {overscore (s)}r(A) ε [max (eps, sr(A)−δ), sr(A)+δ]=[H0, H1], that minimizes the expression:

In an otherwise similar enhanced embodiment of the present invention, step iii. above comprises estimating the unique parameter <o ostyle="single">s</o>r(A) ε [max (eps, sr(A)−δ), sr(A)+δ]=[H0, H1], that minimizes the expression:

In both the directly preceding embodiments, step iv. shows how the value ŝr(A) in Eq. 5 is chosen, namely by setting ŝr(A)={overscore (s)}r(A), where {overscore (s)}r(A) is the result of the minimization problem of Eq. 9 or 10. Like K, the number N in Eq. 9 or 10 is also secret. Although it is possible to select a value of N dependent on K or vice-versa, higher security is achieved when N and K are chosen independently. Thus, the security of the proposed approach resides in the secrecy of set of keys κ={K, N}.

In both the directly preceding embodiments, step iv. shows how the value ŝr(A) in Eq. 5 is chosen, namely by setting ŝr(A)= <o ostyle="single">s</o>r(A), where <o ostyle="single">s</o>r(A) is the result of the minimization problem of Eq. 9 or 10. Like K, the number N in Eq. 9 or 10 is also secret. Although it is possible to select a value of N dependent on K or vice-versa, higher security is achieved when N and K are chosen independently. Thus, the security of the proposed approach resides in the secrecy of set of keys κ={K, N}.

For the purposes of clarity, the following provides detailed proofs of the ability to find an ill-conditioned operator B for a given A, and the ability to find a value {overscore (s)}r(A) ε [H0, H1]. It also provides a discussion of the possible values of key N.

For the purposes of clarity, the following provides detailed proofs of the ability to find an ill-conditioned operator B for a given A, and the ability to find a value <o ostyle="single">s</o>r(A) ε [H0, H1]. It also provides a discussion of the possible values of key N.

In order to prove the existence of {overscore (s)}r(A) ε [H0, H1], minimizing the expression Eq. 10 for a fixed value N, consider the real valued functions h(z):[H0, H1]→<img id="custom-character-00004" he="3.56mm" wi="3.56mm" file="US20070009134A1-20070111-P00001.TIF" alt="custom character" img-content="character" img-format="tif"/>, and g(z):[H0, H1]→<img id="custom-character-00005" he="3.56mm" wi="3.56mm" file="US20070009134A1-20070111-P00001.TIF" alt="custom character" img-content="character" img-format="tif"/> defined as h(z)=sr(B) and

In order to prove the existence of <o ostyle="single">s</o>r(A) ε [H0, H1], minimizing the expression Eq. 10 for a fixed value N, consider the real valued functions h(z):[H0, H1]→<img id="custom-character-00004" he="3.56mm" wi="3.56mm" file="US20070009134A1-20070111-P00001.TIF" alt="custom character" img-content="character" img-format="tif"/>, and g(z):[H0, H1]→<img id="custom-character-00005" he="3.56mm" wi="3.56mm" file="US20070009134A1-20070111-P00001.TIF" alt="custom character" img-content="character" img-format="tif"/> defined as h(z)=sr(B) and

Now, consider h max=max(g(z)) and h min=min(g(z)). If N ε [g(h max), g(h min)] then it exists {overscore (z)} ε [H0, H1] such that g({overscore (x)})=N. This follows from the continuity of g(z) in [H0, H1] and the mean-value theorem of continuous functions.

Now, consider h max=max(g(z)) and h min=min(g(z)). If N ε [g(h max), g(h min)] then it exists <o ostyle="single">z</o> ε [H0, H1] such that g( <o ostyle="single">x</o>)=N. This follows from the continuity of g(z) in [H0, H1] and the mean-value theorem of continuous functions.

<claim-text>11. A method of fragile watermarking according to <claim-ref idref="CLM-00010">claim 10</claim-ref>, wherein ŝr(A) further satisfies ŝr(A)={overscore (s)}r(A) ε [max (eps, sr(A)−δ), sr(A)+δ]=[H0, H1], where δ is a distortion control and eps is machine precision, such that the step of calculating the replacement non-zero singular value comprises calculating substantially the following equation part: </claim-text>

<claim-text>11. A method of fragile watermarking according to <claim-ref idref="CLM-00010">claim 10</claim-ref>, wherein ŝr(A) further satisfies ŝr(A)= <o ostyle="single">s</o>r(A) ε [max (eps, sr(A)−δ), sr(A)+δ]=[H0, H1], where δ is a distortion control and eps is machine precision, such that the step of calculating the replacement non-zero singular value comprises calculating substantially the following equation part: </claim-text>

<claim-text>iii. estimating a unique parameter {overscore (s)}r(A), that minimizes the expression </claim-text>

<claim-text>iii. estimating a unique parameter <o ostyle="single">s</o>r(A), that minimizes the expression </claim-text>

<claim-text>{overscore (s)}r(A) ε [max (eps, sr(A)−δ), sr(A)+δ]=[H0, H1], that minimizes the expression: </claim-text>

<claim-text> <o ostyle="single">s</o>r(A) ε [max (eps, sr(A)−δ), sr(A)+δ]=[H0, H1], that minimizes the expression: </claim-text>

<?in-line-formulae description="In-line Formulae" end="lead"?>Ŝ=diag(s1(A), . . . , sr−1(A), {overscore (s)}r(A)). <?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>Ŝ=diag(s1(A), . . . , sr−1(A), <o ostyle="single">s</o>r(A)). <?in-line-formulae description="In-line Formulae" end="tail"?>

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<?in-line-formulae description="In-line Formulae" end="lead"?>Ii(s,t)=r(s,t)Σi(S(s,t,{right arrow over (Li)})max{right arrow over (Li)}·{right arrow over (Ni)}(s,t),0) [Equation 1]<?in-line-formulae description="In-line Formulae" end="tail"?>

<?in-line-formulae description="In-line Formulae" end="lead"?>Ii(s,t)=r(s,t)Σi(S(s,t,{right arrow over (Li)})max{right arrow over (Li)}·{right arrow over (Ni)}(s,t),0) [Equation 1]<?in-line-formulae description="In-line Formulae" end="tail"?>

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During a second step of normalization, the overall average ion current (E{{overscore (I)}n}) is calculated. Finally, each spectrum is multiplied by a factor, which is equal to the overall average ion current divided by average ion current for that spectrum, namely E{{overscore (I)}n}/{overscore (I)}n. The normalized spectrum becomes

During a second step of normalization, the overall average ion current (E{ <o ostyle="single">I</o>n}) is calculated. Finally, each spectrum is multiplied by a factor, which is equal to the overall average ion current divided by average ion current for that spectrum, namely E{ <o ostyle="single">I</o>n}/ <o ostyle="single">I</o>n. The normalized spectrum becomes

The k-th cluster is denoted Xk={Ãg,n, where n ε {n1, n2, . . . , nN} is the set of N spectra included in the cluster; and k ε {1, 2, . . . , K}, where K is the total number of clusters. The centroid of the k-th cluster ({overscore (X)}k) is defined to be

<entry>{overscore (I)}n</entry>

<entry>{overscore (X)}k</entry>

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