This class provides, within a computer or digital data processing
system, for subject matter represented by a particular arrangement
that includes at least one of the following means: A) components
of an individual complete processor, which may be formed on a single
integrated circuit (IC); B) components of a complete digital data
processing system; C) plural processors; or D) plural digital data
processing systems; wherein the particular arrangement further includes
at least one of the following functions:
1) processing instruction data for specific processor architectures;
2) accessing or retrieving instruction data of a fixed or variable
length from a buffer or other memory and shifting the instruction
data to align it with a physical boundary of a buffer or other memory;
3) locating and retrieving instruction data for processing;
4) determining via internal hardware, firmware or software
operations the meaning of operation codes, control bits, or operands
of instruction data;
5) dispatching instruction data for execution (e.g., designating
a register after resolving data conflicts);
6) dynamically testing instruction data and operands to assess
conflicts related to data or hardware-resource availability (e.g.,
identifying data dependencies or utilization conflicts, attempting
to resolve such dependencies or conflicts, or both); and
7) dynamically controlling the execution, processing, or sequencing
of instruction data within a processor.
SECTION II - NOTES TO THE CLASS DEFINITION
(1)
Note. Instruction data are defined in the glossary for this
class to be data representative of an operation and identifying
its operands, if any.
(2)
Note. Process and apparatus for processing instruction data
that are classified herein are predicated on a particular, identifiable architecture
of a computer or digital data processing system that directs the
nature of the processing. Multiple computer and process coordinating
(e.g., task management, task control) is classified elsewhere.
See SEE OR SEARCH CLASS notes below.
(3)
Note. Register level transactions at the level of the arithmetic
logic unit (ALU-level) or functional unit (FU-level) and logic for
realizing such transactions are often a part of instruction processing,
per se. General purpose, digital logic circuits, however, are
classified elsewhere. See SEE OR SEARCH CLASS notes below.
(4)
Note. Exceptions, interrupts, and traps classified herein
recite the details of the internal operation of the hardware or
the microcode of the processor with only nominal recitation of the
stimulus resulting in the exception, interrupt or trap. Process and
apparatus for queuing or scheduling interrupts or signals in a computer
or digital data processing system are classified elsewhere. See
SEE OR SEARCH CLASS notes below. Process and apparatus directed
to reliability and testing utilizing halts, interrupts, and traps
are also classified elsewhere. See SEE OR SEARCH CLASS notes below.
(5)
Note. Virtual machine or virtual processor is classified
elsewhere. See SEE OR SEARCH CLASS notes below.
(6)
Note. Process and apparatus for dynamically aligning instruction
data are classified herein. Process and apparatus for shifting memory
spaces, such as, boundary alignment related to memory addressing
and page mapping are classified elsewhere. See SEE OR SEARCH CLASS
notes below. Compilers performing static alignment are classified
elsewhere. See SEE OR SEARCH CLASS notes below. Process and apparatus
for aligning for data entry or compacting in cache memory typically
are classified elsewhere. See SEE OR SEARCH CLASS notes below.
(7)
Note. Emulation for decoding instruction data for execution
is classified herein; however, emulation of system component for compatibility
is classified elsewhere. See SEE OR SEARCH CLASS notes below.
Emulation directed to testing is also classified elsewhere. See
SEE OR SEARCH CLASS notes below.
(8)
Note. Process and apparatus for locating and retrieving instruction
data in direct support of an instruction pipeline are classified herein;
however, process and apparatus for accessing and controlling memory
at other higher levels (e.g., cache memory, disk memory, and shared
memory) are classified elsewhere. See SEE OR SEARCH CLASS notes
below.
(9)
Note. Process and apparatus nominally reciting addressing
schemes and address data generation may be classified herein; however,
process and apparatus for generalized address forming, addressing
operands, generating addresses in response to microinstructions,
and addressing in combination with particular memory systems are
classified elsewhere. See SEE OR SEARCH CLASS notes below.
(10)
Note. Process and apparatus for decoding instruction data
to determine their meaning for subsequent execution or decision
making are classified herein; however, generic decoding circuits,
methods, and programs are classified elsewhere. See SEE OR SEARCH
CLASS notes below.
(11)
Note. Process and apparatus for issuing or dispatching of
instruction data to hardware elements internal to a processor for
decoding or executing are classified herein; however, process and
apparatus for dispatching in the field of process control for task
management dealing with process scheduling, load balancing, etc.,
are classified elsewhere. See SEE OR SEARCH CLASS notes below.
(12)
Note. Process and apparatus for dynamically controlling the
issuance or execution of instruction data based on analysis of hardware-resource
availability, hardware-resource utilization, and data dependency are
classified herein; however, processes and apparatus for task resource
management are classified elsewhere. See SEE OR SEARCH CLASS notes
below. Dependency checking performed by a compiler is classified
elsewhere. See SEE OR SEARCH CLASS notes below. Process and apparatus
for enhancing the reliability and availability of functional units
that include determining a fault condition are classified elsewhere.
See SEE OR SEARCH CLASS notes below.
(13)
Note. Process and apparatus for dealing with resource management
problems within a stream of instruction data, generally at the ALU/functional-unit
level are classified herein; however, process and apparatus for resource
management in a manufacturing environment are classified elsewhere.
See the SEE OR SEARCH CLASS notes below.
(14)
Note. Process and apparatus for reserving the use of functional
units at the instruction level of a computer or digital data processing
system are classified herein; however, processes and apparatus for
reserving seats for travel, entertainment, etc. are classified elsewhere.
See SEE OR SEARCH CLASS notes below.
(15)
Note. Process and apparatus utilizing hardware or microcode
for processing and executing instruction data are classified herein; however,
instruction processing being performed by a compiler, by an interpreter,
or by an operating system is classified elsewhere. See SEE OR SEARCH
CLASS notes below. Process and apparatus for high-level processing
of input/output commands are classified elsewhere. See
SEE OR SEARCH CLASS notes below. Process and apparatus for the
sequencing common in computerized numerical controllers (CNC), industrial
controllers, computer driven machining, etc., is classified elsewhere.
See SEE OR SEARCH CLASS notes below.
(16)
Note. Hardwired sequencers are also often referred to as
sequential state machines in the art. They are appropriately classified herein
when they are performing control or sequencing of instruction data
within a processor.
(17)
Note. Process and apparatus for graphic command processing
are classified elsewhere. See SEE OR SEARCH CLASS notes below.
Electronic Digital Logic Circuitry, appropriate subclasses for generic digital logic devices,
circuitry, and subcombinations thereof, wherein nonarithmetical
operations are performed upon discrete electrical signals representing
a value normally described by numerical digits, particularly
subclasses 37+ for programmable circuits such as Programmable
Logic Arrays (PLA) and subclasses 105+ for decoding circuitry.
Communications: Electrical,
subclasses 825 through 825.98for controlling one or more devices to obtain a
plurality of results by transmission of a designated one of plural
distinctive control signals over a smaller number of communication
lines or channels, particularly subclasses 2.1-2.8 for path selection,
subclasses 3.1-3.9 for communication systems where status of a controlled
device is communicated, subclass 825.02 for tree or cascade selective
communication, subclasses 825.2-825.21 for synchronizing selective
communication systems, subclasses 825.52 and 825.53 for addressing
in selective communication system, and subclasses 825.57-825.69
for pulse responsive actuation in selective communication system.
Computer Graphics Processing and Selective Visual
Display Systems, particularly
subclasses 502+ for a computer graphic processor system which includes
plural graphics processors, subclass 522 for graphic command processing
Multiplex Communications, appropriate subclasses for the simultaneous transmission
of two or more signals over a common medium, particularly
subclasses 254+ for network configuration determination, subclasses
351+ for path finding or routing including packet switching,
circuit switching, ATM switching, and subclasses 465+ for
adaptive communication protocol.
Data Processing: Generic Control Systems or Specific
Applications,
subclasses 1 through 89for generic data processing control systems and subclasses
90-306 for specific data processing application.
Data Processing: Vehicles, Navigation, and Relative
Location,
subclasses 1+ for vehicle control, guidance, operation, or indication,
subclasses 200+ for navigation, and subclasses 300+ for
relative location determination.
Data Processing: Measuring, Calibrating or Testing, appropriate subclasses for testing measuring or calibrating,
particularly
subclass 186 for computer and peripheral benchmarking.
Data Processing: Speech Signal Processing, Linguistics,
Language Translation, and Audio Compression/Decompression,
subclasses 1+ for linguistics; subclasses 200+ for speech audio
processing, subclasses 500 through 504 for audio signal time or
bandwidth compression or expansion.
Data Processing: Financial, Business Practice, Management,
or Cost/Price Determination, particularly
subclasses 5+ for reservation, check-in, and booking for reserving
space, subclasses 8+ for scheduling and allocating resources
for administrative functions, and subclasses 64 - 79 for a cryptographically
protected EFT transaction.
Data Processing: Artificial Intelligence,
subclasses 1+ for fuzzy logic hardware; subclass 10 for plural
processing intelligence systems, subclass 11 for artificial intelligence
system having particular user interface; subclasses 12+ for
machine learning system, subclass 14 for adaptive system; subclasses
15+ for neural network; and subclasses 45+ for
knowledge processing system.
Data Processing: Database and File Management
or Data Structures, particularly
subclasses 1 through 10for database or file accessing, subclasses 100-104.1
for database scheme or structure, and subclasses 200-206 for file
or database management.
Electrical Computers: Arithmetic Processing and
Calculating,
subclasses 1+ for electrical hybrid calculating computer, subclasses
100+ for electrical digital calculating computer, and subclasses
800+ for electrical analog calculating computer.
Electrical Computers and Digital Processing Systems:
Multicomputer Data Transferring, appropriate subclassesfor transferring data between plural, spatially
distributed computers or digital data processing systems.
Electrical Computers and Digital Data Processing
Systems: Input/Output, appropriate subclasses for interconnecting or transferring
data among processors, memories, and peripherals for of computers
or digital data processing systems particularly
subclasses 260+ for interrupt processing.
Electrical Computers and Digital Processing Systems:
Memory,
subclasses 1+ for addressing in combination with particular memory systems;
particularly subclass 2 for addressing extended or expanded memory;
subclass 5 for addressing multiple memory modules; subclasses 101+ for
accessing and control of specific memory compositions; subclasses
118+ for cache memory; subclasses 147+ for shared memory
access and control; subclass 159 for memory entry replacement strategies;
subclass 201 for address generation directed to slip control, misalignment,
and boundary alignment; subclass 209 for page address generation
processing; and subclass 212 for address generation by varying bit-length
or size; subclass 214 for operand address generation; and subclass 215
for address formation in response to a microinstruction;
Electrical Computers and Digital Processing Systems:
Support,
subclasses 1 and 2 for computer initialization or configuration;
subclass 100 for reconfiguration; subclasses 150-181 for multiple
computer communication protection by cryptography; subclass 187
for computer program modification detection by cryptography, subclass
188 for computer virus detection by cryptography; subclasses 300-340
for computer power control; and subclasses 400-601 for synchronization
or clock control in a digital data processing.
Error Detection/Correction and Fault
Detection /Recovery, particularly
subclass 707 for synchronization control using an error rate; subclass
731 for a reference timing function or a clock pulse generator
in a scan path testing system; subclass 744 for clock or synchronization
in digital logic testing using a test pattern generator; and subclass
798 for error detection for synchronization control.
Data Processing: Software Development, Installation,
and Management, appropriate subclasses for a software development tool, particularly,
subclasses 140 through 161for compilers and compiler-related dependency checking.
Electrical Computers and Digital Processing Systems:
Virtual Machine Task or Process Management or Task Management/Control, appropriate subclasses for task management or task control,
particularly
subclass 106 for dependency based cooperative processing of multiple
programs working together to accomplish a larger task.
Information Security,
subclasses 1 through 36for information security in computers or digital processing
system.
SECTION IV - GLOSSARY
BUS
A conductor used for transferring data, signals, or power.
COMPUTER
A machine that inputs data, processes data, stores data, and
outputs data.
DATA
Representation of information in a coded manner suitable
for communication, interpretation, or processing.
Address data-Data that represent or identify a source
or destination.
Instruction data-Data that represent an operation and identify
its operands, if any.
Status data-Data that represent conditions of data, digital
data processing systems, computers, peripherals, memory, etc.
User data-Data other than address data, instruction data, or
status data.
DATA PROCESSING
See PROCESSING, below.
DIGITAL DATA PROCESSING SYSTEM
An arrangement of processor(s) in combination with either
memory or peripherals, or both, performing data processing.
ERROR
Manifestation of a fault as an undesired event that occurs
when actual behavior deviates from the behavior that is required
by initial specifications.
FAILURE
Manifestation of an error as a nonperformance of an expected
system service as required by the initial specifications.
FAULT
A flaw in a functional unit (hardware or software).
INFORMATION
Meaning that a human being assigns to data by means of the
conventions applied to that data.
MEMORY
A functional unit to which data can be stored and from which
data can be retrieved.
PERIPHERAL
A functional unit that transmits data to or receives
data from a computer to which it is coupled.
PROCESSING
Methods or apparatus performing systematic operations upon
data or information exemplified by functions such as data or information
transferring, merging, sorting, and computing (i.e., arithmetic
operations or logical operations).
(1)
Note.In this class, the glossary term data is used to modify
processing in the term data processing; whereas the term digital
data processing system refers to a machine performing data processing.
(2)
Note.In an effort to avoid redundant constructions, in this
class, where appropriate, the term address data processing is used
in place of address data data processing.
PROCESSOR
A functional unit that interprets and executes instruction data.
RECOVERY
Responding to a fault in a system by either returning
a system to a previous level of correct operation, achieving a degraded
level of correct operation, or safely shutting down the system.
SECURITY
Extent of protection for system hardware, software, or data
from maliciously caused destruction, unauthorized modification,
or unauthorized disclosure.
This subclass is indented under the class definition. Subject matter comprising a particular arrangement of (a)
elements of an individual complete processor which may be formed
on a single integrated chip, (b) components of a complete digital
data processing system, (c) plural processing elements, (d) plural
processors, or (e) plural digital data processing systems where
processing is performed on a generic instruction or process.
(1)
Note. This subclass and its indents require more than nominal
recitation of the architecture of processing elements or operations.
(2)
Note. Implementation of a generic instruction within a particular
instruction set is classified here.
(3)
Note. Architecture based instruction processing including
specific instruction implementation, such as, branching, store
multiple, etc. are classified elsewhere. See SEE OR SEARCH THIS CLASS,
SUBCLASS notes below.
Communications: Electrical,
subclasses 825 through 825.98for controlling one or more devices to obtain a
plurality of results by transmission of a designated one of plural
distinctive control signals over a smaller number of communication
lines or channels, particularly subclasses 2.1-2.8 for path selection,
subclasses 3.1-3.9 for communication systems where status of a controlled
device is communicated, subclass 825.02 for tree or cascade selective
communication, subclasses 825.2-825.21 for synchronizing selective
communication systems, subclasses 825.52 and 825.53 for addressing,
and subclasses 825.57-825.69 for pulse responsive actuation.
Computer Graphics Processing and Selective Visual
Display Systems,
subclasses 502+ , for a computer graphic processor system which includes
plural graphics processors.
Multiplex Communications, for the simultaneous transmission of two or more signals
over a common medium where the transmitted data is generic to the
transmission activity, particularly
subclasses 351+ for time division multiplex (TDM) switching, subclasses
475 for asynchronous TDM communications including addressing, and
subclasses 498+ for time division bus transmission.
Electrical Computers: Arithmetic Processing and
Calculating,
subclasses 100+ and particularly subclasses 200+ for an
electric digital calculating computer which may utilize processor structure
similar to that contained herein.
Electrical Computers and Digital Processing Systems:
Multicomputer Data Transferring, appropriate subclassesfor data transfer between plural spatially distributed
computers or digital data processing systems.
Electrical Computers and Digital Data Processing
Systems: Input/Output,
subclasses 100+ for particular intrasystem connecting (e.g., bus
transaction processing) not included in a particular processing
architecture, and subclasses 260+ for general interrupt processing.
Data Processing: Software Development, Installation,
and Management,
subclasses 149 and 150 for program code translating or compiling
for multiprocessor system.
This subclass is indented under subclass 1. Subject matter including specificadaptation of the architecture
or structure which operates on one-dimensional data arrays.
Electrical Computers: Arithmetic Processing and
Calculating,
subclasses 100+ and particularly subclasses 200+ for an
electric digital calculating computer which may utilize processor structure
similar to that contained herein.
This subclass is indented under subclass 2. Subject matter which includes an intermediate structure
linking a scalar processor with a vector processor.
Electrical Computers and Digital Processing Systems:
Multicomputer Data Transferring, appropriate subclassesfor data transfer between plural complete spatially
distributed computers or digital data processing systems.
This subclass is indented under subclass 4. Subject matter which is directed to specific structure or
operation to screen out access to a particular location in a vector
register.
This subclass is indented under subclass 1. Subject matter comprising four or more identical processing
elements (e.g., cells) joined in a two-dimensional or higher arrangement.
Electrical Computers: Arithmetic Processing and
Calculating,
subclasses 100+ and particularly subclasses 200+ for an
electric digital calculating computer which may utilize processor structure
similar to that contained herein.
Electrical Computers and Digital Data Processing
Systems: Input/Output,
subclasses 100+ for particular intrasystem connecting (e.g., bus
transaction processing) not included in a particular array processing
architecture.
This subclass is indented under subclass 11. Subject matter wherein the identical processing elements
are joined in a 3-or - greater dimensional pattern.
This subclass is indented under subclass 11. Subject matter which controls the structure joining the
processing elements by partitioning the array into groups of processing
elements.
This subclass is indented under subclass 11. Subject matter which controls the structure joining the
memory within an individual array processor element or associated
with an individual array processor element.
Electrical Computers and Digital Processing Systems:
Multicomputer Data Transferring,
subclasses 221+ for reconfiguring in a multi-computer data transfer
network.
Electrical Computers and Digital Data Processing
Systems: Input/Output,
subclass 104 for intra-system configuring not included in a
particular processing architecture.
Electrical Computers and Digital Processing Systems:
Support,
subclass 100 for reconfiguring (e.g., changing system setting)
in a digital data processing system.
This subclass is indented under subclass 16. Subject matter wherein overall operation or process of the
array processor is directed toward a particular purpose.
(1)
Note. Included here, for example, is generic pattern matching
not elsewhere provided for.
(2)
Note. Pattern matching for image processing is classified
elsewhere.
This subclass is indented under subclass 16. Subject matter wherein the array processor performs a calculation
when all required data is present (data-driven).
(1)
Note. This would include a wavefront array processor.
This subclass is indented under subclass 16. Subject matter wherein data moves between the identical
processing elements in accordance with a global reference timing
signal.
This subclass is indented under subclass 1. Subject matter comprising an architecture which determines
a group of upcoming instructions which do not mutually interfere
with each other and issues or dispatches this group simultaneously.
(1)
Note. Excluded herein is specific instruction implementation
such as branching, store multiple, etc. See SEE OR SEARCH THIS CLASS,
SUBCLASS: notes below.
(2)
Note. Implementation of a generic instruction within a particular
instruction set is classified here.
This subclass is indented under subclass 1. Subject matter comprising an architecture which includes
compiler scheduled issuing of multiple opcodes per instruction.
(1)
Note. Excluded herein is the specifics of the compiler.
This subclass is indented under subclass 1. Subject matter wherein a plural processor structure performs
a calculation when all required data is present (data-driven) or
when other processors request a calculation result (demand-driven).
This subclass is indented under subclass 25. Subject matter which is directed to specific structure or
operation to perform detecting or pairing dependent upon intended
destination, a particular identification tag or data itself.
This subclass is indented under subclass 25. Subject matter including a data driven interface with specific
memory structure to enhance the data flow capability of the processor.
This subclass is indented under subclass 1. Subject matter including a particular architecture having
two or more physically separate processors performing different
tasks with shared resources such that their combined work contribute
to a common goal.
(1)
Note. Subject matter including a distributed processing system
having significant multicomputer data transfer is classified elsewhere.
See SEE OR SEARCH CLASS below.
(2)
Note. Subject matter including a computer task management
or control system having significant process scheduling is classified
elsewhere. See SEE OR SEARCH CLASS below.
Electrical Computers and Digital Processing Systems:
Multicomputer Data Transferring,
subclass 201 for distributed data processing having significant
multicomputer data transfer.
Electrical Computers and Digital Processing Systems:
Virtual Machine Task or Process Management or Task Management/Control,
subclasses 102 through 108for process scheduling in a computer task management
or control system.
This subclass is indented under subclass 30. Subject matter wherein the physically separate processors
include a primary processor (master) controlling the operation of
a secondary processor (slave).
(1)
Note. Controlling of data transfer between master/slave
processors is classified elsewhere.
Computer Graphics Processing and Selective Visual
Display Systems,
subclass 504 for a computer graphic processing system including master/slave
processors.
Electrical Computers and Digital Processing Systems:
Multicomputer Data Transferring,
subclasses 208+ for specific data transferring in a
master/slave computer.
This subclass is indented under subclass 1. Subject matter comprising a CPU on a single integrated circuit
chip or on plural integrated chips or in plural discrete units which
provide serial processing.
Electrical Computers: Arithmetic Processing and
Calculating,
subclasses 100+ and particularly subclasses 200+ for an
electric digital calculating computer which may utilize processor structure
similar to that contained herein.
This subclass is indented under subclass 32. Subject matter including an auxiliary processor which provides
a supplemental function for or other assistance to a primary processor.
(1)
Note. Details of the application or algorithm performed on
the coprocessor are classified elsewhere. See,
for example, SEE OR SEARCH CLASS below.
This subclass is indented under subclass 34. Subject matter wherein the auxiliary processor is particularly
configured to perform high speed data manipulations.
(1)
Note. Details of the application or algorithm performed on
the Digital Signal Processor are classified elsewhere. See, for
example, SEE OR SEARCH CLASS below.
This subclass is indented under subclass 32. Subject matter wherein particular internal structure of
the processor is provided which allows interfacing from the processor
to an external device.
Electrical Computers and Digital Data Processing
Systems: Input/Output,
subclass 1 for input/output data processing and
subclasses 305-317 for interface architecture intra-system connection.
This subclass is indented under subclass 38. Subject matter wherein an internal processor mode may be
changed by an external means connected to the processor by an electrical
contact.
This subclass is indented under subclass 38. Subject matter wherein the processor receives a synchronization
or interrupt signal from an outside source.
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