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| Class 711 | ELECTRICAL COMPUTERS AND DIGITAL PROCESSING SYSTEMS: MEMORY |
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![[List of Pre Grant Publications for class 711 subclass 1]](../as.gif) | ![[List of Patents for class 711 subclass 1]](../ps.gif) | 1 | ADDRESSING COMBINED WITH SPECIFIC MEMORY CONFIGURATION OR SYSTEM |
| | 2 |  Addressing extended or expanded memory |
| | 3 | Addressing cache memories |
| | 4 | Dynamic-type storage device (e.g., disk, tape, drum) |
| | 5 | For multiple memory modules (e.g., banks, interleaved memory) |
| | 6 | Virtual machine memory addressing |
| | 100 | STORAGE ACCESSING AND CONTROL |
| | 101 | Specific memory composition |
| | 102 |  Solid-state read only memory (ROM) |
| | 104 | Solid-state random access memory (RAM) |
| | 107 | Ferrite core |
| | 108 | Content addressable memory (CAM) |
| | 109 | Shift register memory |
| | 111 | Accessing dynamic storage device |
| | 115 | Detachable memory |
| | 116 | Bubble memory |
| | 117 | Hierarchical memories |
| | 118 | Caching |
| | 119 |  Multiple caches |
| | 120 |  Parallel caches |
| | 121 | Private caches |
| | 122 | Hierarchical caches |
| | 123 | User data cache and instruction data cache |
| | 124 | Cross-interrogating |
| | 125 | Instruction data cache |
| | 126 | User data cache |
| | 127 | Interleaved |
| | 128 | Associative |
| | 129 | Partitioned cache |
| | 130 | Shared cache |
| | 131 | Multiport cache |
| | 132 | Stack cache |
| | 133 | Entry replacement strategy |
| | 137 | Look-ahead |
| | 138 | Cache bypassing |
| | 140 | Cache pipelining |
| | 141 | Coherency |
| | 147 | Shared memory area |
| | 148 | Plural shared memories |
| | 149 | Multiport memory |
| | 150 | Simultaneous access regulation |
| | 151 | Prioritized access regulation |
| | 152 | Memory access blocking |
| | 153 | Shared memory partitioning |
| | 154 | Control technique |
| | 155 | Read-modify-write (RMW) |
| | 156 | Status storage |
| | 157 | Interleaving |
| | 158 | Prioritizing |
| | 159 | Entry replacement strategy |
| | 161 | Archiving |
| | 163 | Access limiting |
| | 165 | Internal relocation |
| | 166 | Resetting |
| | 167 | Access timing |
| | 170 | Memory configuring |
| | 200 | ADDRESS FORMATION |
| | 201 | Slip control, misaligning, boundary alignment |
| | 202 | Address mapping (e.g., conversion, translation) |
| | 203 | Virtual addressing |
| | 204 | Predicting, look-ahead |
| | 206 | Translation tables (e.g., segment and page table or map) |
| | 209 | Including plural logical address spaces, pages, segments, blocks |
| | 210 | Resolving conflict, coherency, or synonym problem |
| | 211 | Address multiplexing or address bus manipulation |
| | 212 | Varying address bit-length or size |
| | 213 | Generating prefetch, look-ahead, jump, or predictive address |
| | 214 | Operand address generation |
| | 215 | In response to microinstruction |
| | 216 | Hashing |
| | 217 | Generating a particular pattern/sequence of addresses |
| | 219 | Incrementing, decrementing, or shifting circuitry |
| | 220 | Combining two or more values to create address |
| | 221 | Using table |
| E-SUBCLASSES | ||
| The following subclasses beginning with the letter E are E-subclasses. Each E-subclass corresponds in scope to a classification in a foreign classification system, for example, the European Classification system (ECLA). The foreign classification equivalent to an E-subclass is identified in the subclass definition. In addition to US documents classified in E-subclasses by US examiners, documents are regularly classified in E-subclasses according to the classification practices of any foreign Offices identified in parentheses at the end of the title. For example, "(EPO)" at the end of a title indicates both European and US patent documents, as classified by the EPO, are regularly added to the subclass. E-subclasses may contain subject matter outside the scope of this class.Consult their definitions, or the documents themselves to clarify or interpret titles. |
| | E12.001 | ACCESSING, ADDRESSING OR ALLOCATING WITHIN MEMORY SYSTEMS OR ARCHITECTURES (EPO) |
| | E12.002 | Addressing or allocation; relocation (EPO) |
| | E12.003 | With multidimensional access, e.g., row/column, matrix, etc. (EPO) |
| | E12.004 | With look-ahead addressing means (EPO) |
| | E12.005 | User address space allocation, e.g., contiguous or noncontiguous base addressing, etc. (EPO) |
| | E12.006 | Free address space management (EPO) |
| | E12.007 | In block-addressed memory (EPO) |
| | E12.009 | Garbage collection, i.e., reclamation of unreferenced memory (EPO) |
| | E12.013 | Multiple users address space allocation, e.g., using different base addresses, etc. (EPO) |
| | E12.014 | Using tables or multilevel address translation means (EPO) |
| | E12.015 | Addressing variable-length words or parts of words (EPO) |
| | E12.016 | In hierarch |
